TLK10031: Clock distribution

Hello Yaser, thank you for your reply. Will be waiting for your feedback.

Hi Yaser, any updates on this?

Hi Mohammad,

Sorry for the late reply. See below for my notes on your questions.

1. Does our clock connection look correct?

• Yes the Jitter cleaner is not necessary as long as VCOX is guaranteed to be with the spec listed in the datasheet (i.e. FHSoffset & VID) and have low noise/jitter. See below quote from datasheet section 8.2.2 Detailed Design Procedure.
  • "A differential reference clock must be provided to either the REFCLK0P/N or REFCLK1P/N input port. The clock signal should be AC-coupled and have a differential amplitude between 250 mV and 2000 mV peakto-peak. For 10GBASE-R applications, the clock frequency should be either 156.25 MHz or 312.5 MHz and have an accuracy of 100 ppm. Because jitter on the reference clock can transfer through the TLK10031 PLLs and onto the serial outputs, it is best to keep the reference clock’s jitter as low as possible (that is, under 1 ps from 10 kHz to 20 MHz) in order to meet the requirements of IEEE 802.3."

2. We are confused about the block diagram in the datasheet shown in the second image. Does the jitter cleaner outputs the VCXO or the CLKOUT to the FPGA?  Please explain the reference block diagram connection.

• CLKOUT is output to the FPGA. The Jitter cleaner would take in both signals separately and output both separately. 

3. If our connections are correct, what are the procedures to get CLKOUT to work and test the PHY-FPGA XAUI interface?

• I would first begin by verifying that the below registers have the expected configuration for your application. Could you describe more what issue you are seeing with CLKOUT? Are you not seeing any output at all?
  • REFCLK_SW_SEL bit field
  • LS_REFCLK_SEL bit field
  • REFCLK_FREQ_SEL_1 bit field
  • REFCLK_FREQ_SEL_0 bit field
  • CLK_CONTROL register

4. From our research, we found out that CLKOUT will output half the frequency of the VCXO. So. do we need to use 312.5MHz oscillator instead of 156.25MHz? If needed, we can generate 156.25MHz from an on-chip FPGA PLL and just ignore CLKOUT. So basically PHY is driven by the VCXO and FPGA is driven by another oscillator. Should this configuration work? Do we need any way of synchronization between both PHY and FPGA in this case?

• The recommend configuration is to have CLKOUT connected to FPGA instead of separate PLL. CLKOUT output frequency could change dynamically depending on your system. CLK_CONTROL register the output CLK can be selected to be in the configurations listed in CLKOUT_SEL[3:0] bit field. Also as you mentioned please synchronization between the two clock (if separate) would be needed and can be hard to achieve. 

Dear Malik, thank you so much for your answer.

Our main issue right now is that for the XAUI core (+MDIO controller) inside the FPGA to operate correctly, it requires a 156.25 MHz free running clock. How can we get this clock from the TLK10031 after power up and before sending any MDIO configuration? (because MDIO on the FPGA core needs 156.25MHz clock to operate in the first place!)

Hello Malik,

Thanks for your help.

What about replacing the 156.25MHz oscillator with a 312.5MHz? Then configure the PHY to output 312.5MHz divided by 2 ? We can implement a standalone MDIO controller on the FPGA to do this if it can solve the issue.