TMDS181: HDMI2.0 sink compliance impossible with intra- and inter-pair skew?

Sjoerd

Please see Figure 12 of the TMDS181 datasheet. HDMI2.0 spec defines the skew at the connector level, TMDS181 defines the skew at the device level.

Thanks
David

Dear David,

Thanks for your quick response. Thanks for pointing to Figure 12, which will be helpful for this discussion.

I realize that I asked multiple questions in one post; in order not to lose track of them, I numbered them hereafter. Could you please refer to the question number when answering?

PCB Margin

Your explanation is indeed how I understand it: HDMI2.0 specifies skew at the HDMI connector (TTP1), whereas the TMDS181 datasheet specifies the skew at the IC pins (TTP2).

First of all: (Question 1) Do I understand correctly that this 'sink' application of the TMDS181 is an intended application of the device?

Between TTP1 and TTP2 there are a trace, AC coupling capacitors and, in our case, ESD protection and a common mode filter. Let us call all of this 'the PCB'.

Let me try to create an overview of the specifications, and calculate how much margin there is left for the PCB:

Parameter	TTP1 (HDMI2.0)	TTP2 (TMDS181)	Margin (left over for the PCB between TTP1 and TTP2)
Intrapair skew tolerance	0.15Tbit+112ps	112ps	-0.15Tbit
Interpair skew tolerance	0.2Tcharacter+1.78ns	1.8ns	-0.2Tcharacter+20ps

 

Intrapair skew

For the intrapair skew, I find negative margin. This means that between connector and TMDS181, we need to reduce the intrapair skew. To my knowledge, this only way to reduce intrapair skew is a common mode filter. Hence, a common mode filter is required to achieve HDMI2.0 compliance with the TMDS181 acting as a sink. (Question 2) Is this reasoning correct?

On the TMDS181 EVM, I do not see a common mode input filter. (Question 3) Does this mean that the EVM is not HDMI2.0 compliant, or is another technique used for achieving compliance?

The worst (longest) T_bit occurs at the lowest pixel rate (25.175 MHz, if I am not mistaken), so this is about 40 ns. This means that at 25.175 Mbps, the common mode filter must be able to reduce 0.15T_bit+112ps = 0.15*(1/25.175e6)+112e-12 = 6.07ns of intrapair skew to 112ps. (Question 4) Is this calculation correct?

Interpair skew

For the interpair skew tolerance, the datasheet mentions tRX_INTER as maximum value. This seems strange to me, because there is no minimum value, so the actual tolerance could also be zero. (By contrast, tRX_INTRA is a minimum value, which is logical.) For the reasoning below, I suppose this is a typesetting mistake, and it should have been the minimum value. (Question 5) Do you agree?

Whether the margin is positive or negative depends on the character clock (1/10th of the pixel clock). The best case PCB margin is obtained for the smallest T_character, so for the highest datarate, which is 6.0 Gbps:

-0.2T_character+20ps = -0.2*(1/(6e9/10)) + 20e-12 = -333ps + 20ps = -313ps

So even in the best case, the PCB margin is negative. (Question 6) Is this calculation correct?

I do not now of any way to reduce interpair skew (because you do not know in advance whether one pair leads or lags the other pair). (Question 7) How to achieve HDMI2.0 compliance with this seemingly impossible margin?

Please do feel free to point out errors in my reasoning. I hope I am mistaken and/or that there is a typo in the datasheet, because we would like to apply the TMDS181 in our products!

Thanks in advance,
Sjoerd Op 't Land

Sjoerd

For intra-pair skew, the spec for TMDS181 at TTP2 is 112ps, this gives you 0.15Tbit margin for the FR4 PCB trace plus the AC coupling caps. If you add. If you add them together, then you will have 0.15Tbit + 112ps at TTP1.

Same for the inter-pair skew, the FR4 PCB trace plus the AC coupling caps have 0.2Tcharacter + 20ps margin.

Thanks
David

Dear David,

Thanks again for your swift response.

First of all, do you agree that less skew is better (and more skew is worse)?

Then, do you agree that typically (except for common mode filters) skew becomes worse (=more) in the propagation direction of a signal?

For example, if we would have 10ps of intrapair skew at TTP1, and add 5ps by the PCB, we would have 15ps of intrapair skew at TTP2. Right?

Therefore, I would expect the TTP2 skew tolerance to be higher than the TTP1 skew tolerance.

(Your reasoning would be kind of correct for the output, because I would expect the skew at TTP3 to be lower than that at TTP4.)

Please indicate where my reasoning is mistaken, thanks again and in advance,
Sjoerd

Sjoerd

Please give me a day and let me understand how TMDS1881 was initially characterized. I see what you are saying and I need to find out this difference.

Thanks
David

Dear David,

Thanks in advance for your investigation!

Would you have any news? If the matter seems more complicated that expected; no problems, but could you give a new estimate of when you could answer our initial question?

Thanks again,
Sjoerd

Sjoerd

The inter-pair skew in the datasheet should read: T_RX_INTER (MAX) : 0.2*Tcharacter +1.78 ns for 3.4G < Rbit < 6.0G.

For intra-pair skew, datasheet should read: 0.15Tbit + 112ps for 3.4G < Rbit < 6.0G.

And the value should be spec'ed at the connector, not at the pin level.

Thanks
David

Dear David,

Thanks for your clarification. What do you mean by 'the value should be spec'ed at the connector not at the pin level'? The TMDS datasheet cannot specify anything about the skew values at the connector, because it is about the IC, not about the PCB. Right?

This is how I understand things with your clarification:

Parameter	TTP1 (HDMI2.0)	TTP2 (TMDS181)	Margin (left over for the PCB between TTP1 and TTP2)
Intrapair skew tolerance	0.15Tbit+112ps	0.15Tbit+112ps (for 3.4G < Rbit < 6.0G)	0
Interpair skew tolerance	0.2Tcharacter+1.78ns	0.2Tcharacter+1.78ns	0

This is a problem, because there is 0 margin. Especially for the interpair skew tolerance, this is a problem, because 0 skew is almost impossible to obtain.

Or were the values obtained with a simulation including a typical PCB? If so, what where the characteristics of this typical PCB?

The reason I am asking is that we need to define the inter/intra-pair skew that our PCB between TMDS181 and connector may introduce. We would like to define our PCB first-time-right, and not go through many protyping-measurement cycles. (Moreover, a compliance measurement does not prove that our product will always be compliant, because we cannot measure all temperature-process corners. By contrast, you (TI) can do this in simulation, and that is why the datasheet values are important to us.)

I still do not understand why T_RX_INTER is a maximum value (while T_RX_INTRA) is a minimum value). If there is no minimum value, I suppose it can be 0 too. Right? If so, this means we cannot guarantee product compliance for all IC process-temperature corners. Could you explain?

Thanks again,
Sjoerd 

Sjoerd

The number in the datasheet needs to be updated.

For inter-pair skew, TMDS181 can handle around 2Tcharacter of skew. At 6G, this will be ~3.33ns. Spec is 0.2Tcharacter + 1.78ns which is 2.11ns.

For intra-pair skew, we typically recommends 5mil skew tolerance.

Thanks
David

Dear David,

Good to hear that it seems to be the datasheet, not the component ;)

Is our need clear to you? We would like to use the TMDS181 IC, on a PCB that we will design ourselves. Of course, we will perform compliance measurements on one prototype instance, but this should merely be a check. The measurement is just one sample in the temperature-process space, so it is perfectly possible that the measurement passes, but that we will ship a product (with an IC from another batch) that will fail tomorrow at a client's. Therefore, we need to have a correct reasoning based on (worst case) component specifications, that leads to compliant product specifications. That is why datasheet values are very important to us. Does this make sense?

It is not yet clear to me: does the TMDS181 datasheet specify (a) signal properties on the IC pins (TTP2) or (b) on the HDMI connector (TTP1)? Could this also be clarified in the datasheet by referring to Figure 6 or 12 (and mentioning TTP1/2)?

In case (a), I would expect the datasheet to be updated to show 2Tcharacter minimum inter-pair skew tolerance. Am I right? How about the actual intra-pair skew tolerance?

In case (b), what are the properties of the connector and PCB used to simulate the values in the datasheet? What inter- and intra-pair were introduced on your simulation PCB? We need some way to compare your numbers (with your reference PCB) to our PCB.

Thanks again and in advance,
Sjoerd

Sjoerd

Please accept my friendship request and I will send you our TMDS181 EVM layout. This is the EVM we used that physically passed HDMI compliance test. So you can use the EVM layout as the starting point.

The data sheet specify the point at the IC pin, but tested at the connector. Again, the number in the data sheet is not correct, it needs to be 2Tcharacter max. From my previous response, it will give you ~1.2ns margin assuming worst case of 0.2Tcharacter + 1.78ns at the connector. Assuming 180ps/in FR4 propagation delay, this will give ~6in inter-pair skew margin.

For intra-pair skew, please follow TI recommendation of 5mil skew.

As long as the design is not done right at the limit of the TMDS181, you have plenty of margin across the temperature/process/voltage corner.

Thanks
David

Dear David,

Thank you for pointing to the EVM layout, we already had a look at that.

For the inter pair, I understand that the new datasheet will contain 2Tcharacter as minimum interpair skew tolerance. (Minimum, right? Otherwise, there may be PVT cases where the tolerance is less.)

For the intra pair, I would guess the new datasheet to contain 112.9 ps as minimum intrapair skew. (0.9ps being the value corresponding to 5mil.)

We need to base our design correctness on datasheet values. Do you have an idea when the revised datasheet will be published?

Thanks in advance,
Sjoerd

Sjoerd

I would define 2Tcharacter as max skew tolerance. If the design goes beyond 2Tcharacter, then TMDS181 will not able to compensate for the skew in its retimer mode.

I need to work with our datasheet team to have the datasheet updated.

Thanks

David

Dear David,

Indeed, 2Tcharacter is the maximum signal inter pair skew you guarantee to accept. This means that the tolerance of your IC is minimally 2Tcharacter. (There may be ICs that tolerate more 2Tcharacter, but never less.)

Compare, for example with the intra pair skew tolerance (which is shown as a minimum value, an rightly so).

If you disagree, could you please explain why one tolerance is a minimum value and the other is a maximum value?

Thanks in advance,
Sjoerd

Dear David,

Did you already have the time to look at my last post?

Thanks in advance,
Sjoerd

Sjoerd

I am sorry that I was out of office last week. Did Brian's answer address your question? If so, I will mark his answer as resolved.

Thanks
David

Dear David,

No problem. I have a few remaining questions before this thread can be closed:

1. Do you agree with Brian's answer (that both intra and inter pair skew tolerances should be minimum values)?
2. Could you confirm the definitive values (both higher than the actual values) that will appear in the next version of the datasheet?
3. Do you have an estimate when the new version of the datasheet will be available?

Thanks in advance,
Sjoerd

Sjoerd

I agree with Brian's response, both inter and intra skew should be minimum.

For the inter-pair skew, please use 2Tcharacter as the design guideline. For intra-pair skew, please use 5mil as the design guideline.

I will notify you once the datasheet has been updated.

Thanks
David

Dear David,

Thanks for your answer. 'Design guide' sound a bit non-binding...

We would like to base our design reasoning on datasheet numbers, so we would prefer that the table be updated with the actual numbers that the simulation was run with (which comprised some PCB inter/intra-pair skew, right?).

Thanks in advance,
Sjoerd

Sjoerd

I understand, but TMDS181 has also been designed into multiple projects in the past without any issues.

Thanks
David