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DS110DF410: Complete Reset without power cycling, channel register reset bits

Kawai
Guru 19775 points
Part Number: DS110DF410

Hi Team,

We would like to fully reset the DS110DF410 operation of each channel without power cycling.
We are asking this because customer is facing a CDR unlock issue which they could not recover even applying the register settings again + CDR Reset.
They are always needed to disconnect and connect the input cable.

Q1). Could channel register REG 0x00 [2] = 1 fully RESET the device function and the operation at that timing ?

Q2). Would it be better to write REG 0x00 = 0x0F to make sure all the function including the state machine to be RESET ?

Q3). Are the REG 0x00 [3:0] auto reset bits which would automatically return to "0" when user wrote to "1" ?
 -> I wanted to know if user would need to write back "0" especially for bit [3], [1], and [0].

Q4). Should we first apply REG 0x00 [2] = "0", then, apply REG 0x00 = 0x0B ?
 -> I am asking this because Register Reset to default value may be applied faster than RST_CORE, RST_REFCLK, or RST_VCO.

Best Regards,
Kawai

  • 0
    TI__Guru* 93670 points
    Hi Kawai-San,
    Please note comments below:
    Q1). Reg 0x00[2] resets all channel registers to their default values. To restart CDR state machine, we should use channel reg 0x0A[3:2].
    Q2). There is not a need to reset other bits.
    Q3). It is preferred to set reg 0x00[2] and then reset this pin.
    Q4). It is recommended to set and reset reg 0x00[2] only. Reseting other bits have not been fully utilized so I would stay away from reseting other bits.

    1). I am not sure if you tried to force signal detect off and on. This should restart the CDR state machine.

    2). Did CDR unlock occurred after sometimes that it was locked?

    3). Do we know what caused device to get unlocked?

    4). Did you turn off lock qualifiers at reg 0x2F(ppm_check_en and FLD_check_en), 0x0A(SBT_EN), and 0x3E(HEO/VEO lock mon) to see what may have caused device to go unlock?

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Guru 19775 points

    Hi Nasser-san,

    > Q1). Reg 0x00[2] resets all channel registers to their default values. To restart CDR state machine, we should use channel reg 0x0A[3:2].
    Both "CDR Reset" or "register reset and then register re-programming" could not make the device to lock to the input signal.

    > Q2). There is not a need to reset other bits.
    Please allow me to clarify if register reset (REG 0x00 [2] = "1") would be functionally equivalent to power cycling the device (fully reset) for the channels.

    > Q3). It is preferred to set reg 0x00[2] and then reset this pin.
    REG 0x00[2] resets register value to default. That means, this bit will be automatically restored with "0".
    My question was that if REG 0x00 [3], [1], [0] are required to write back to "0".

    > Q4). It is recommended to set and reset reg 0x00[2] only. Reseting other bits have not been fully utilized so I would stay away from reseting other bits.
    If these bits are not recommended to be change, I would strongly request to change the [3], [1], and [0] descriptions to RESERVED.

    > 1). I am not sure if you tried to force signal detect off and on. This should restart the CDR state machine.
    No we haven't tried force signal detect OFF and ON. Why wouldn't the CDR Reset work to reset the CDR state machine ?

    > 2). Did CDR unlock occurred after sometimes that it was locked?
    No, it rarely fails at first link-up. When it fails they needed to disconnect and connect the cable for normal operation.
    They had tried, register reset and re-programming (including CDR Reset), however, no improvement.

    > 3). Do we know what caused device to get unlocked?
    Not yet. We need the register dump information at this failure, however, it is difficult to reproduce this issue.

    > 4). Did you turn off lock qualifiers at reg 0x2F(ppm_check_en and FLD_check_en), 0x0A(SBT_EN), and 0x3E(HEO/VEO lock mon) to see what may have caused device to go unlock?
    First, we need customer to reproduce this issue for further tests.

    Best Regards,
    Kawai

  • 0 in reply to Kawai
    TI__Guru* 93670 points
    Hi Kawai-San,
    Q2). Resetting registers is not the same as power cycling. when you power off and on signal detect goes from in-active to active and power gets turned off and on to different circuit blocks so theses are not the same.
    Q3). Reg 0x00[3] and Reg0x00[1:0] are not self clearing and are required to be set to "0".
    Q4). I agree. Sure we would or should have set these to RESERVED as you noted.
    1). CDR reset and signal detect off and on side effects are not the same. When we reset CDR signal detect state has not changed. But if we force signal detect off and on, first signal detect state has changed AND we are restarting CDR state machine because of the signal detect state change. This is just another experiment to try.
    2). If I understand you correctly, in the lock failure case, CDR lock is achieved but after sometimes it loses lock - without signal going away? Did I describe this correctly?
    3&4). If possible - through the email - please send me the overall test setup.
    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Guru 19775 points
    Hi Nasser-san,

    Thanks for your continuous support.

    I will send you an email. Let's discuss offline for the detail.

    Best Regards,
    Kawai