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LMH1981: Hsync Output Pulse Width of LMH1981

KAEDE KUDO
Expert 2700 points
Part Number: LMH1981
Other Parts Discussed in Thread: LMH1983

Hello,

I have a question about LMH1981.

[Q]

My customer has a two boards equipped with LMH1981 and LMH1983.

They use analog video input: NTSC.

Board A: Hsync Output Pulse width=2.41usec.

               LMH1983 PLL1 Locked.

Board B: Hsync Output Pulse width=2.25usec.

               LMH1983 PLL1 Unlocked.

Q1: Is the phenomenon that the above pulse width is related to the fact that PLL1 does not lock?

Q2: Is the above difference in pulse width not a problem as the LMH1981?

Best Regards,

Kaede Kudo

  • 0
    TI__Genius 11900 points

    Hello Kaede,

    Is the difference in the pulse width for Hsync output from LMH1981 / input to LMH1983 the only difference between the boards?

    The requirements for Hsync as mentioned in the LMH1983 datasheet are as follows:

  • 0 in reply to Vibhu Vanjari
    Expert 2700 points

    Hello Vidhu,

    Thank you for confirming.

    This problem can be solved by changing the Lock Step Size of LMH1983 to Unlock and increasing the Window Size.

    When the customer examined the differences between the boards, I confirmed that the pulse width of the LMH1981's Hsync was different, and wondered whether it was related to the LMH 1983 Lock / Unlock.

    I think that LMH1983 compares the falling edge of Hsync, so the pulse width is not relevant.
    In addition, I changed the Window Size and improved it, so I think that it may be due to the difference between the Hsync Jitter.

    Does the rising edge of Hsync also affect Lock?
    Is my understanding that changing the Lock Step Size and Loss of Lock Threshold will allow you to lock when the amount of jitter is large?

    Best Regards,

    Kaede Kudo

  • 0 in reply to KAEDE KUDO
    TI__Genius 11900 points

    Hello Kaede,

    The typical output pulse width for NTSC format listed in the LMH1981 datasheet is 2.5us, this could have caused issues that were solved by your increasing the horizontal sync output pulse width.

    Does the rising edge of Hsync also affect Lock?

    The LMH1981 datasheet also mentions the following in the "Horizontal Sync Output" section:

    "HSync was optimized for excellent jitter performance on its leading edge because most video systems are negative-edge triggered. When HSync is used in a positive-edge triggered system, like an FPGA PLL input, it must be inverted beforehand to produce positive-going leading edges. The trailing edge of HSync should never be used as the reference or triggered edge. This is because the trailing edges of HSync are reconstructed for the broad serration pulses during the vertical interval."

    Please ensure that your system abides with the above. If it doesn't this may be related to the rising edge effecting the lock.

    Is my understanding that changing the Lock Step Size and Loss of Lock Threshold will allow you to lock when the amount of jitter is large?

    Yes, please refer to section "8.3.6 Lock Determination" of the LMH1983 datasheet, this explains how.

  • 0 in reply to Vibhu Vanjari
    Expert 2700 points

    Hello Vidhu,

    Thank you for your reply and sorry for my late reply.

    I understood your comment,

    And my customer resolved this problem by changing Lock Step Size and Loss of Lock Threshold.

    Thank you for your cooperation.

    Best Regards,

    Kaede Kudo