I have a multi-drop M-LVDS network prototyped with 4-layer boards with a clock transceiver and a data transceiver for each of 19 nodes. The transmission line is CAT 5e with 100 ohm terminations at each end. The length of twisted-pair wiring is approximately 7" between nodes. The two nodes at each end of the network are attached to microcontrollers, for at total of four microcontroller. Each microcontroller has a SPI-master only driver that connects to the transmitter MLVDS ICs one each for clock and data, and each microcontroller has a SPI-slave only receiver that is connected to the MLVDS receiver. With a clock of 80MHz (12.5ns bit time) I am seeing a longer delay for the data than the clock, 6ns on the differential side and an additional 2ns from single-ended transmit signal to received single-ended signal when compared to the clock. The difference in length between the twisted pairs due to different twists per foot (21 vs 32) doesn't account for the 6ns delay as its only ==. I expect to see similar delays on clock and data signals. The result is a large number of CRC errors due to the data shifting a bit time. Do you have any ideas why this is happening and how to prevent it?
