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DS92LV2421: DS92LV2421 CLKIN Requirement

Part Number: DS92LV2421

Hello team,

 

I got a question from the customer.

Our customer is developing the system with DS92LV2421/2422.

They are facing the issue that 2422 sometimes loses the PLL Lock. (12/250 failure systems)

Regarding the failure system, they noticed that CLKIN has a jitter.

 

Is there any detail CLKIN specification like Cycle-to-cycle jitter?

As far as I checked the datasheet(6.9 Timing Requirements). I couldn't find the detail information about it. The customer inputs the CLKIN without SSC.

 

Now the customer is checking the channel link with BIST function.

However, we're assuming that there's no problem on the channel link side.

Because they already evaluated the cable swap test.

 

I would really appreciate it if your team would support this ASPS.

 

Best Regards,

Kazuki Kitajima

  • Hello Kitajima-san, 

    Can you tell me what frequency you are using?

  • Hi Sally-san,

    They are using this device @ 65MHz.

    Please let me know if you need further more information.

    Thank you,

    Kazuki kitajima

  • Hi Kitajima-san, 

    I can only give you guidelines based on theory regarding the jitter tolerance. 
    Based on the Deserializer input jitter tolerance (pg 16) =  .9 UI for jitter freq < 2 MHz and Serializer output total jitter (pg 15) = .28 UI, if you subtract the two, the total input jitter tolerance overall = .62 UI 

    Based on the Deserializer input jitter tolerance (pg 16) =  .5 UI for jitter freq > 6 MHz and Serializer output total jitter (pg 15) = .28 UI, if you subtract the two, the total input jitter tolerance overall = .22 UI 

    1 UI = 1/ (28 * CLK) = 549 ns 

    The total input jitter tolerance overall would include jitter from the cable jitter, interconnect jitter, trace jitter, via jitter, clk jitter, etc. 

    This is the guideline I can provide you with.