Hi Team,
further question to ask based on my previous E2E post , is there's any layout trace length limitation of LVDS output((Y0p~Y3p,Y0m~Y3m)?
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Hi Team,
further question to ask based on my previous E2E post , is there's any layout trace length limitation of LVDS output((Y0p~Y3p,Y0m~Y3m)?
Hello Andy,
We do not have a strict limitation here. The guidance would be to base this off the trace insertion loss for your stackup to ensure that the receiving device's DC input thresholds can be met at the other end. Also keep in mind that increased routing distance will make the design more prone to noise coupling from external sources or other signals on the board.
Best Regards,
Casey