Other Parts Discussed in Thread: XIO2001
1187 XIO2001 ZGU EVM REV C
I am currently developing a solution using the XIO2001. Unfortunately, our present design does not allow the PC to detect the bridge. In my efforts to troubleshoot, I have stumbled across some inconsistencies between the EVM and supporting documentation. In the EVM there are three signals to each PCI slot which have trace length matching. First of which is the PCI_CLK, this was stated in the documentation. However, the other two, nREQ and nGNT, I have been unable to find supporting documentation as to why this was performed.
I am wondering if this is required? Why it was done on the EVM? What are these signal lengths matched to?
Thank you.
