TPD1S414: Question on timing requirements

Jeff Coletti

Part Number: TPD1S414

Hi All

My customer noticed what i believe is a discrepancy in the data sheet. if tdelay is 20msec and tss is 25ms how come the rise time in figure 8 shows 27ms? Data sheet also states teh start up time is tdelay plus tsoftstart?

Thanks

Jeff Coletti

over 5 years ago

0 Adam Mc Gaffin over 5 years ago

TI__Mastermind 30000 points

Hi Jeff,

Let me look into this item, and I'll provide a response to you next week

0 Michael Tan over 5 years ago

TI__Expert 8420 points

Hi Jeff,

The figure 8 only show the voltage but haven't show the ACK signal , the tss is start from 20% VBUS_sys to ACK signal set low.

0 Jeff Coletti over 5 years ago in reply to Michael Tan

TI__Expert 8755 points

Hi Michael

I still do not understand, I thought /ACK would occur after vbus_conn valid. Where does the 25msec ss in the picture, I can see the delay of 20 msec from time 0 to vbus_sys full on. Also why no current if you are powering a 2.2uf cap? Do you have a full timing diagram you can send me via email?

Thanks

Jeff

0 Michael Tan over 5 years ago in reply to Jeff Coletti

TI__Expert 8420 points

Hi Jeff,

I don't have the full timing diagram but I can apply the EVM to confirm this point.

To be ware the Tss and Tdelay is only show the typical value but not the max. Any way , I need sometime to confirm with the EVM and give the reply to you soon.

0 Michael Tan over 5 years ago in reply to Michael Tan

TI__Expert 8420 points

Hi Jeff,

I have send you the mail, the soft start time definition is from Vpwr to ACK set low. I will close this topic here.

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TPD1S414: Question on timing requirements