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HD3SS3202: PCIe Gen2 Clock and Data Switch

Hao Wang14
Expert 4415 points
Part Number: HD3SS3202
Other Parts Discussed in Thread: LMK00334, CDCI6214

Hi Team,

Can HD3SS3202 be used as PCIe Gen2 clock and data switch? Because there are three devices A/B/C, sometimes A will connect to B, the other times A will connect to C, so we need a switch for both clock and data transmission. 

If so, may I know the additive phase jitter?

If not, could you please recommend the best solution for this usecase?

Thanks and Best Regards!

Hao

  • 0
    TI__Guru** 119660 points

    Do you want to switch signal between PCIe clk and Data?

  • 0 in reply to Brian Zhou
    TI__Expert 4415 points

    Hi Brian,

    Yes, we want to switch both clock and data.

    Thanks and Best Regards!

    Hao

  • 0 in reply to Hao Wang14
    TI__Mastermind 43795 points

    Hi Hao.

    You can use the HD3SS3202 to switch a PCIe clock between two devices (B or C in your case).

    I would use 1 HD3SS3202 for the Clock signal only.  I would use additional HD3SS3202 devices to Mux/Demux the data lines.

    By keeping the clock separate there will be little if any phase noise addition to the clock signal.

    Another option would be to use the LMK00334 PCIe clock buffer to produce multiple copies of the PCIe Reference Clock signal.

    Regards,

    LEe

  • 0 in reply to Lee Sledjeski
    TI__Expert 4415 points

    Hi Lee,

    Thanks for confirming. We have CDCI6214 to have four channel 100MHz HCSL output, but five outputs are needed, so we are considering using HD3SS3202 as mux for additional clock output. 

    The max phase jitter of CDCI6214 for PCIe Gen3 is 0.5ps, HD3SS3202 will bring additive phase jitter in the signal chain. The max jitter for PCIe Gen3 is 1ps, so the additive phase jitter of HD3SS3202 is critical, the datasheet only tells there is very little added jitter, could you please help confirm the additive jitter of HD3SS3202? 

    Thanks and Best Regards!

    Hao

  • 0 in reply to Hao Wang14
    TI__Mastermind 43795 points

    Hi Hao,

     

    The HD3SS3202 will not directly contribute to phase jitter in a 100MHz clock system.  Additive Rj or phase jitter is a reflection of active circuitry within a design, the HD3SS3202 is a passive switch.  An additive Rj or phase jitter specification is given for active devices or equalizers to describe the internal circuit effects on Rj.  Since the HD3SSxxxx devices are entirely passive components with no active gain.  This type of measurement would show an extremely low additive jitter number, basically at the noise floor of the measurement system.

     

    I would expect an additive phase noise measurement of this device to produce a result of << 0.5ps using PCIe system clock electrical characteristics as the source signal.

     

    Regards,

    Lee