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DP83848J: No reponse from phy after MDIO message.

6389249
Prodigy 40 points
Part Number: DP83848J

I am using an Arty board (Digilent) and I am trying to communicate with the DP83848JSQ from an FPGA.

I've already confirmed the PHY is working correctly through another design, but I am specifically trying to read and write PHY registers over mdio/mdc, something I have not tested elsewhere.

However, I'm seeing some interesting behavior occur.

I'm attempting to send the message wire [13:0] message = 14'b00000100000110; which should instruct the PHY at address 00001 to send the contents of register zero back to the fpga. I only have one PHY connected to the FPGA and according to Digilent, the PHY is set to address 0001 at power-up.

My process right now is to send a reset signal to the PHY through the reset pin and follow up with the 32 clock cycles shortly after. I'm actually sending more like 60 to be safe as I know there is some time I have to wait between reset and sync.

After the sync, I'm sending 1 bit of the message at a time through mdio at the negedge of each mdc clock cycle. 

After I send the last bit of the message, I am putting mdio into a hi-Z state for receiving. The problem is, I don't seem to receive anything. mdio does not get pulled down by the PHY like it should. 

Here is a screenshot of that (mdc is 10 Mhz in this example. I have not noticed a change with a slower/faster clock) : 

Zoomed in:

But, If I send the message wire [13:0]  message = 14'b00000000000110; which sends to PHY address 0x0 which is not what expect from the ARTY, mdio gets pulled down by the PHY for some period of time, but I don't see any data. 

Here is a screenshot of that (mdc is 10 Mhz in this example. I have not noticed a change with a slower/faster clock) : 

It gets even more confusing than that as if I change the message to send to an invalid address the PHY should not respond to, wire [13:0] message= 14'b00000110000110;, mdio never gets pulled down, suggesting that when using the correct address, the PHY is doing something. 

Here is a screenshot of that (mdc is 10 Mhz in this example. I have not noticed a change with a slower/faster clock) : 

And a more zoomed-in version of the same waveform:

  • 0
    TI__Genius 9920 points

    Hello,

    Just wanting to walk through some typical debugging questions but just to confirm, have you strapped your PHY address to your expected value? Are you also able to use our USB2MDIO tool to ensure that the reads and writes are going through properly? Our tool is available on the web for you to download and confirm if that is possible.

    Thanks

    Cecilia

  • 0 in reply to Cecilia Reyes
    Prodigy 40 points

    Hi,

    I'm unable to use the USB2MDIO as I'm controlling the PHY with an FPGA. The address should be strapped correctly as this is a well-known FPGA dev board and I have two of them showing the same symptoms, so something wrong with the hardware seems unlikely.

    According to the IEEE spec, should the device respond to address 00000 like it should, no matter the strapped address?

    The only thing I can think of is that I do not reset the MDC clock. Should the MDC only become active sometime after hard reset of the PHY?

    Thanks,

    Maxwell Kunes

  • 0 in reply to 6389249
    TI__Genius 9920 points

    Hi Maxwell,

    Thats correct we have a minimum time for the XI clock to be stable before MDC preamble. Have you confirmed that your clock is stable for at least 167ms? The spec is in the power up timing section of our datasheet.

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    Prodigy 40 points

    Cecilia,

    I'm fairly certain X1 is stable at power up as this is a development board made by Digilent and that the other functions of the PHY work properly, just not MDIO. 

    If I'm reading correctly, the other criteria is that X1 needs to be stable for 167 ms before MDC can occur. I'm likely sending an MDC preamble too early.

    However, would resetting the PHY using the reset pin override this after power-up resolve this issue? Because I have tested resetting the PHY using the reset pin and waiting for 3-4 uS before sending a preamble with the same problems I described above. Even in this case must X1 be stable for 167 ms original on startup before MDC can occur?

  • 0 in reply to 6389249
    Prodigy 40 points

    Update:

    I was under the impression that X1 was populated on the Arty dev board. It is not. I guess I need to feed that from the FPGA. Sorry about that. That is almost certainly why my mdio is not functioning.

    Thanks,

    Maxwell Kunes