Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 32 subscribers
  • Views 366 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS92LV2421: LV24EVK01 Clock Input

Cem Gecgel
Prodigy 90 points
Part Number: DS92LV2421
Other Parts Discussed in Thread: LV24EVK01

Hi Professional,

I am currently trying to use ser / des (LV24EVK01) implementation on a certain video panel application.I give the input clock (25 MHz) signal of serializer from FPGA. But the LOCK and PASS pin of the deserializer are not going high. It doesn't work with the signal which is posted below. I tried giving some other signals as clock source from some other sources and they worked well. I am awere the input pins of the ser / des pair accepts max 3.3V, some other oscilloscope generated 5V 10MHz clock signal worked as well. I am uploading 2 signals which are generated from FPGA, one of them is 5V and other one is 3.3V. Could you enlighten me out what could be possibly wrong in my situtation?

  • 0
    TI__Genius 12866 points

    Hi Cem,

    Could you verify there's proper grounding and proper termination when measuring the clock signal? 

    The two clock signals are both distorted in the picture. 

    The scope also shows the frequency is 12.5Mhz. 

    For the second picture, the clock frequency is changing and you can see the max is 1.4G and min is 3.2Mhz.

    Please make sure the FPGA clock output is stable.

    Best Regards,

    Charley Cai