Other Parts Discussed in Thread: SIGCONARCHITECT, DS150DF1610
Dear TI team,
I’m currently testing a custom board design using DS125DF1610 retimer, with a 12,5 Gbit/s signal (8 lanes) coming in.
I’m seeing differences with the different boards (tested 5 so far) being able to lock CDR on the signal. Some can’t lock at all, some can lock on only a few lanes, some can lock on all 8 lanes.
I already tried to set respective “debug” settings in 0x0C[3] and 0X2F[2:1] register using SigConArchitect, which leads to some more channels being able to achieve lock. (But the eye diagram is horrible)
I measured the incoming eye diagrams close to the BGA pins (via) with a high-bandwidth scope. It’s not great, but generally we appraise it as being good enough, at least compared to what contemporary FPGAs are able to process.
So my questions are:
- Is the DS125DF1610 really suitable to process a 12,5 Gbit/s signal or is it critical since it’s “at the edge” of what is specified in the datasheet? Would the DS150DF1610 be a better choice?
- Is there any criterion for the minimum eye height and width that the retimer is able to lock on at 12,5Gbit/s?
- Does the selection of the reference clock (25 MHz vs 125 MHz vs. 312,5 MHz) have any influence on this issue?
Thanks and best regards,
Valentin
