TLK2501: Receiver Clock recovery PLL bandwidth

Hi Mita, see inputs below.

1. PLL questions
   
   • Receiver Clock recovery PLL bandwidth
     • Around 3 MHz
       

   • Order of the PLL
     • Info not available
       
   • Dumping factor of the PLL
     • Info not available
       
2. Please let me know the receiver side Eye mask
   
   • Minimum VID spec is 200mV
     
   • Jitter tolerance is 0.6UI; jitter is Differential input jitter, random + deterministic, PRBS pattern at zero crossing
     
3. If GTX/CLK clock quality influence no the receiver performance
   
   • Yes, of course
     
   • See guidelines below
     

Reference Clock (TXCLK) Timing Requirements, over recommended operating conditions (unless otherwise noted)

Cordially,

Rodrigo Natal

HSSC Applications Engineer