DP83867IR： Default value of 0x01D5 register

Hi Team,

I'm waiting for an answer to this question.

My understanding is that the default value can be read if it is not written to a register, since it is not in the strap settings.

Regards,

Kenji

Hi Kenji,

Have you made sure that the proper procedure to read extended registers is being followed?

I would recommend referencing section 8.4.2.1 Extended Address Space Access of the Datasheet.

Please let me know if you want any clarification on this section.

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Joe,

I know how to read the extended registers.

I'm getting this question from one of my customers.

When reading the defaults, there are some production lot that read the correct default value and others that read 0x0000.

I have my doubts about the lot that reads 0x0000.

Regards,

Kenji

Hi Kenji,

I will reach out to other team members to find out why this default value is different for said lot and the impact of this differing value.

I hope to get you a response by the end of business Thursday (4/29).

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Kenji,

I have talked with the team and I have a couple of follow-up questions.

What is the reason they are trying to read this register? 

Are other datasheet registers being read as expected?

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Joe,

My customer did not intentionally read only this register, but dumped the whole register.

Since the register values differ from lot to lot, the customer asks the question.

Except for the following two addresses, both lots read the correct values.

Lot : 84A33YWG4

0x01C0-01D0: Initial value 0x0000

0x01D5: Initial value 0x0000

Lot: 02A0CVWG4

0x01C0-01D0: Initial value There is data that is not 0x0000

0x01D5: Initial value 0xf500

Best Regards,

Kenji

Hi Kenji,

The team is looking into your question internally and I hope to get back to you by next Tuesday (5/4).

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Kenji,

I have reached out to the design team and they are still looking into this and I hope to get you an update by Thursday (5/6).

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Kenji,

To help narrow down the source of the issue I have the following questions:

On the phys reading these registers as 0, are all other register read correctly?

Do these phys link-up without any issues and they are able to do the data transfer?

Did they try to write any of these register and are able to do that?

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Joe,

Write and read operations are normal.

And there is no problem except for the 0x01C0-01D0 and 0x01D5 registers.

I would like to get a confirmation that the default value of the reserve address data is different, but it does not cause any malfunction.

The customer has not found any operational problems with the PHY so far.

Regards,

Kenji

Hi Kenji,

Are you using the 64-pin QFP package? This register being all 0's for the QFP package will not impact the performance of the device. 

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Joe,

Thank you for your answer.

My customer is using DP83867IRPAPT (64-pin QFP package).

I'm relieved to see that there is no impact on performance.

I would like to know the reason why the default value 0 occurred.

Regards,

Kenji

Hi Joe,

Sorry, some information has been changed.

The following with the correct default values were not working properly.

　Lot number 02A0CVWG4

　0x01C0-01D0: Initial value There is data that is not 0x0000

　0x01D5: Initial value 0xf500

The customer has checked 10pcs and all 10pcs are malfunctioning.

Fault conditions
　After connecting to a specific device and entering the link-up state, the link-down state occurs at irregular intervals (several seconds to several hours).

　Some devices will continue to link down, while others will link up normally after another second.

However, it does not seem to occur on some devices, so I think there may be a problem with the oncoming connected device.

The link down occurs because the amount of jitter in the signal input to the PHY is rather large (but within the jitter specification).

The reason is unknown, but if you set bit 12 of the 0x01CF register (default value: 0x1708) to 0 (0x1708→0x0708), the link down will not occur.

Even though 0x01CF is RESERVED, the phenomenon disappears.

I would like to know what the reason for this is.

Regards,

Kenji

Hi Kenji,

I am communicating with design for this issue and I hope to get back to you by the end of business Thursday (5/13).

In the meantime, I would like to ask how did you or your customer figure this out (set bit 12 of the 0x01CF)? And have you strapped rx_ctrl to mode 3?

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Kenji,

How did you or your customer figure this out (set bit 12 of the 0x01CF)? And have you strapped rx_ctrl to mode 3?

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Joe,

I will report the results to you as follows

・0x01CF Register

The customer confirmed the difference between the registers of 84A33YWG4 Lot and 02A0CVWG4 Lot.

After changing the BITs of the different registers in order, the customer was able to improve the situation by chance.

・RX_CTRL

The strap setting is not done, but bit[7] is rewritten to 0.

　02A0CVWG4 0x10b0 → 0x1030

I would like to know why if I set bit 12 (default value: 0x1708) of the 0x01CF register to 0 (0x1708 -> 0x0708), the link down does not occur!

Regards,

Kenji

Hi Kenji,

Thank you for confirming how this difference was observed. We are still having design look into this. Thank you for your patience and I hope to get you a response by Tuesday of next week (5/18).

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Joe,

I'm waiting for your answer.

How is your progress?

Regards,

Kenji

Hi Kenji,

Our Design team is still looking into this issue. I will update you as soon as possible.

Kind Regards,

Joe

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

Hi Kenji, 

Thank you for you patience. Design would like some additional details on your issue.

Here are their questions:

• What is the VDDIO level?
• What is the value of the pull-up resistor on MDIO?
• What is the MDC frequency used?

If available, can they perform one or all of the following experiments?

• Exp – 1
  • After power-up perform a pin reset
  • Read the registers multiple (say at least 10) times i.e. Read 0x01c0 register 10 times, followed by 0x01c1 10 times and so on
• Exp – 2
  • Try writing the default value mentioned in the datasheet to this registers and read back and check if they read the correct value or still read all 0s
• Exp – 3
  • Reduce the MDC frequency to say <1MHz and try reading these registers

Joe-san,

Answer as follows.

　What is the VDDIO level?　→　3.3V

　What is the value of the pull-up resistor on MDIO?　→2.2kΩ

　What is the MDC frequency used?　→　2.5MHｚ

Exp - 1: Which value is the correct value to read? Are registers 0x01c0 and 0x01c1 hidden registers that are not user-used?

Exp - 2: The default values for 0x01c0 and 0x01c1 are unknown since they are not listed in the datasheet.

Exp - 3: The customer plans to implement this at 500 kHz. One moment, please.

Regards,

Kenji