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C6678 DSP- DP83867 PHY SGMII Link up Issue

ABDULKERIM ALTUNTAS
Prodigy 200 points
Other Parts Discussed in Thread: DP83867E

Hello everyone,

We have a custom board containing C6678 DSP which is connected to a DP83867 PHY via the SGMII interface. The problem is about the link up in the SGMII interface. The MDI side of the PHY is connected to a PC through a CAT-5 ethernet cable. The MDI side is auto-negotiated to 1000Mbps with no problems. We observed two different cases:

a)  When the PHY is connected to the PC and the MDI side auto-neg is completed, the SGMII auto-negotiation and link-up ALWAYS FAILS.

b)  While the PHY is disconnected from the PC, i.e. the MDI side of the PHY is open-circuit, then SGMII link-up is SOMETIMES ESTABLISHED. So is the SGMII auto-negotiation.

What is the problem here? Which register settings should be done on C6678 and DP83867 to get the SGMII interface work correctly? Any suggestion is greatly appreciated.

Regards,

Abdulkerim

  • 0
    TI__Mastermind 19780 points
    Hi Abdulkerim,

    Is the application for 6-wire or 4-wire(CDR) SGMII? In case you are using 4-wire SGMII with C6678, please see this thread for initializing C6678 w/ 4-wire(CDR).

    e2e.ti.com/.../960603

    Have you also reviewed section 9 in the following C6678 document? www.ti.com/.../sprabc1.pdf

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 200 points
    Hi Rob,

    Our application is 4-wire(CDR) SGMII. We reviewed the document as you suggested. In addition, according to the document, we tried some different settings on the DSP/SGMII side like different CDR threshold, adaptive equalizer, swing and de-emphasis settings. Unfortunately, none of them resulted in a successful SGMII link.

    During our investigation, we found -interestingly- that if the PC side PHY is forced to 100Mbps & Half Duplex mode, then the SGMII auto-negotiation is completed and the link is succesfully established. Following it, we were able to connect to a server running on the PC and exchange data with the server program. At this point, we observed that the DP83867 automatically advertises 100Mbps & HD on the SGMII side to comply with the MDI side link. However, if the PC side PHY is forced to 100Mbps & Full Duplex, then the SGMII link gets never up.

    What might be the issue that prevents the completion of the auto-neg between the DP83867 and C6678 when the MDI side is 100Mbps & FD? Let me put the question another way: In terms of the SGMII link and auto-neg, what is the difference between the 100Mbps & FD and 100Mbps & HD MDI side link?

    Best regards,
    Abdulkerim
  • 0 in reply to ABDULKERIM ALTUNTAS
    Prodigy 200 points
    Hi again,

    I forgot to add that throughout our investigations the DP83867 is always set to auto-negotiate on the MDI and SGMII sides.

    Thanks,

    Abdulkerim
  • 0 in reply to ABDULKERIM ALTUNTAS
    TI__Mastermind 19780 points
    Hi Abdul,

    I need a bit more information from you to try and pinpoint your issue.

    When you say forcing the link on the PC side, are you doing this through Windows?

    Is it possible to force other speeds at half duplex with your PC settings? 10M HD, 1000M HD

    How do you check that the PHY has link on the MDI side? Are you using LED indication or PHY register indication?

    How are you checking the status of the SGMII link? Using the C6678 register or the DP83867 register 0x37?

    Is the C6678 in SGMII slave mode?

    When the MDI resolves between HD and FD, the abilities reported during SGMII auto-negotiation process are different. Your C6678 may be failing SGMII auto-negotiation based on the link duplex status. I need to know the answers to the questions above in order to make a better evaluation of the problem.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 200 points
    Hi Rob,

    Thanks for your reply.

    The answers to your questions are as follows:

    1) Yes, we force the link through Windows.
    2) We tested both 10M HD and FD. Enabling the 10M SGMII on the DP83867, both settings worked with no problems.
    3) We check the MDI side link from Windows. We observe that if the PC side is set to auto-negotiate then the MDI link comes up as 1.0Gbps which seems that there is no problem in the MDI side connection.
    4) To check the SGMII link we use both C6678 and DP83867 (register 0x37). As we stated earlier, when the MDI side is set to 100M HD, then SGMII link can be seen to be set on both sides(DSP and PHY).
    5) The C6678 operates in SGMII slave mode as it is recommended by the sprugv9 document. (Keystone GbE Switch Subsystem User Guide)

    Meanwhile, we tested the SGMII link with another PHY(Marvell 88E1512). For all MDI link cases(10M HD&FD, 100M HD&FD and 1000M FD), C6678 and 88E1512 PHY were able to establish the SGMII link successfully. This observation led us to think that the problem seems to be with DP83867 PHY.

    Best regards,

    Abdulkerim
  • 0 in reply to ABDULKERIM ALTUNTAS
    Prodigy 200 points
    A minor note for Q2 => Since our PC does not support 1000M HD, we could not test it. But we know that 1000M FD setting doesn't work.

    Thanks,
    Abdulkerim
  • 0 in reply to ABDULKERIM ALTUNTAS
    TI__Mastermind 19780 points
    Abdulkerim,

    Are you using DP83867 devices you procured from the estore? This part is relatively new and I want to make sure you have the production devices. Can you send a picture of the top marking of the DP83867 device you are using?

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 200 points

    Hi Rob,

    The device we are using is a sample. Please find the picture of the top marking below.

    If we didn't interpret it wrong, the top marking reads as:

    DP83867E TI 58I A96Z G4

    Thanks,

    Abdulkerim

  • 0 in reply to ABDULKERIM ALTUNTAS
    TI__Mastermind 19780 points
    Hi Abdulkerim,

    Please elongate the SGMII auto-negotiation timer in register 0x31. I recommend using value 0x10d0 in register 0x31.

    When you have a link established in FD and HD, please read out register 0x38. This register should follow the bit definition in the SGMII standard tx_config_Reg[15:0]. This register is what the PHY is sending to the MAC.

    Please also read out register 0xDC for me in both conditions.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 200 points

    Hi Rob,

    We elongated the SGMII auto-negotiation timer to 800us, that is Register 0x31 is set to 0x10D0.  Unfortunately, nothing has changed. As in the original SGMII auto-negotiation timer value (2us),  100Mbps HD case works fine whereas the SGMII link never comes up in the 100Mbps FD case.

    For completeness, I have dumped all the PHY registers -including the ones you asked us- and copied them into a text file which is attached to this reply.

    Hope it will help you.

    Best regards,

    Abdulkerim

    DP83867_RegisterDump.txt 
    DP83867 100Mbps Half Duplex Case Register Dump
Note: SGMII link between C6678 and DP83867 is successfully established.

PHY Reg: 0x0		Read: 0x1140 
PHY Reg: 0x1		Read: 0x796d 
PHY Reg: 0x2		Read: 0x2000 
PHY Reg: 0x3		Read: 0xa231 
PHY Reg: 0x4		Read: 0x1e1 
PHY Reg: 0x5		Read: 0x4c81 
PHY Reg: 0x6		Read: 0x67 
PHY Reg: 0x7		Read: 0x2001 
PHY Reg: 0x8		Read: 0x0 
PHY Reg: 0x9		Read: 0x300 
PHY Reg: 0xa		Read: 0x0 
PHY Reg: 0xd		Read: 0x401f 
PHY Reg: 0xe		Read: 0x15 
PHY Reg: 0xf		Read: 0x3000 
PHY Reg: 0x10		Read: 0x5848 
PHY Reg: 0x11		Read: 0x5f02 
PHY Reg: 0x12		Read: 0xffff 
PHY Reg: 0x13		Read: 0x1c40 
PHY Reg: 0x14		Read: 0x29c7 
PHY Reg: 0x15		Read: 0x0 
PHY Reg: 0x16		Read: 0x0 
PHY Reg: 0x17		Read: 0x40 
PHY Reg: 0x18		Read: 0x6150 
PHY Reg: 0x19		Read: 0x4444 
PHY Reg: 0x1a		Read: 0x2 
PHY Reg: 0x1e		Read: 0x2 
PHY Reg: 0x1f		Read: 0x0 
PHY Reg: 0x25		Read: 0x400 
PHY Reg: 0x31		Read: 0x10b0 
PHY Reg: 0x32		Read: 0xd3 
PHY Reg: 0x33		Read: 0x0 
PHY Reg: 0x37		Read: 0x3 
PHY Reg: 0x43		Read: 0x7a0 
PHY Reg: 0x6e		Read: 0x801 
PHY Reg: 0x6f		Read: 0x50 
PHY Reg: 0x71		Read: 0x0 
PHY Reg: 0x72		Read: 0x0 
PHY Reg: 0x86		Read: 0xd7 
PHY Reg: 0xd3		Read: 0x0 
PHY Reg: 0xfe		Read: 0xe721 
PHY Reg: 0x134		Read: 0x1000 
PHY Reg: 0x135		Read: 0x0 
PHY Reg: 0x136		Read: 0x0 
PHY Reg: 0x137		Read: 0x0 
PHY Reg: 0x138		Read: 0x0 
PHY Reg: 0x139		Read: 0x0 
PHY Reg: 0x13a		Read: 0x0 
PHY Reg: 0x13b		Read: 0x0 
PHY Reg: 0x13c		Read: 0x0 
PHY Reg: 0x13d		Read: 0x0 
PHY Reg: 0x13e		Read: 0x0 
PHY Reg: 0x13f		Read: 0x0 
PHY Reg: 0x140		Read: 0x0 
PHY Reg: 0x141		Read: 0x0 
PHY Reg: 0x142		Read: 0x0 
PHY Reg: 0x143		Read: 0x0 
PHY Reg: 0x144		Read: 0x0 
PHY Reg: 0x145		Read: 0x0 
PHY Reg: 0x146		Read: 0x0 
PHY Reg: 0x147		Read: 0x0 
PHY Reg: 0x148		Read: 0x0 
PHY Reg: 0x149		Read: 0x0 
PHY Reg: 0x14a		Read: 0x0 
PHY Reg: 0x14b		Read: 0x0 
PHY Reg: 0x14c		Read: 0x0 
PHY Reg: 0x14d		Read: 0x0 
PHY Reg: 0x14e		Read: 0x0 
PHY Reg: 0x14f		Read: 0x0 
PHY Reg: 0x150		Read: 0x0 
PHY Reg: 0x151		Read: 0x0 
PHY Reg: 0x152		Read: 0x0 
PHY Reg: 0x153		Read: 0x0 
PHY Reg: 0x154		Read: 0x0 
PHY Reg: 0x155		Read: 0x0 
PHY Reg: 0x156		Read: 0x0 
PHY Reg: 0x157		Read: 0x0 
PHY Reg: 0x158		Read: 0x0 
PHY Reg: 0x159		Read: 0x0 
PHY Reg: 0x15a		Read: 0x0 
PHY Reg: 0x15b		Read: 0x0 
PHY Reg: 0x15c		Read: 0x0 
PHY Reg: 0x15d		Read: 0x0 
PHY Reg: 0x15e		Read: 0x0 
PHY Reg: 0x15f		Read: 0x0 
PHY Reg: 0x161		Read: 0xc 
PHY Reg: 0x16f		Read: 0x15 
PHY Reg: 0x170		Read: 0xc0d 
PHY Reg: 0x172		Read: 0x0 
PHY Reg: 0x180		Read: 0x752 
PHY Reg: 0x1a7		Read: 0xef20 
PHY Reg: (MMD3_PCS_CTRL) 0x0		Read: 0x1140 

/* Re-reading some special registers once again */
PHY Reg: 0x0013		Read: 0x0 
 
PHY Reg: 0x0010, Read: 0x5848
 
PHY Reg: 0x0031, Read: 0x10b0
 
PHY Reg: 0x0037, Read: 0x1

PHY Reg: 0x0037, Read: 0x1
 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 

****************************************************

DP83867 100Mbps Full Duplex Case Register Dump
Note: No SGMII link between C6678 and DP83867 is established.

PHY Reg: 0x0		Read: 0x1140 
PHY Reg: 0x1		Read: 0x796d 
PHY Reg: 0x2		Read: 0x2000 
PHY Reg: 0x3		Read: 0xa231 
PHY Reg: 0x4		Read: 0x1e1 
PHY Reg: 0x5		Read: 0xcd81 
PHY Reg: 0x6		Read: 0x6f 
PHY Reg: 0x7		Read: 0x2001 
PHY Reg: 0x8		Read: 0x6001 
PHY Reg: 0x9		Read: 0x300 
PHY Reg: 0xa		Read: 0x0 
PHY Reg: 0xd		Read: 0x401f 
PHY Reg: 0xe		Read: 0x15 
PHY Reg: 0xf		Read: 0x3000 
PHY Reg: 0x10		Read: 0x5848 
PHY Reg: 0x11		Read: 0x7c02 
PHY Reg: 0x12		Read: 0xffff 
PHY Reg: 0x13		Read: 0x1c44 
PHY Reg: 0x14		Read: 0x29c7 
PHY Reg: 0x15		Read: 0x0 
PHY Reg: 0x16		Read: 0x0 
PHY Reg: 0x17		Read: 0x40 
PHY Reg: 0x18		Read: 0x6150 
PHY Reg: 0x19		Read: 0x4444 
PHY Reg: 0x1a		Read: 0x2 
PHY Reg: 0x1e		Read: 0x2 
PHY Reg: 0x1f		Read: 0x0 
PHY Reg: 0x25		Read: 0x400 
PHY Reg: 0x31		Read: 0x10b0 
PHY Reg: 0x32		Read: 0xd3 
PHY Reg: 0x33		Read: 0x0 
PHY Reg: 0x37		Read: 0x2 
PHY Reg: 0x43		Read: 0x7a0 
PHY Reg: 0x6e		Read: 0x801 
PHY Reg: 0x6f		Read: 0x50 
PHY Reg: 0x71		Read: 0x0 
PHY Reg: 0x72		Read: 0x0 
PHY Reg: 0x86		Read: 0xd7 
PHY Reg: 0xd3		Read: 0x0 
PHY Reg: 0xfe		Read: 0xe721 
PHY Reg: 0x134		Read: 0x1000 
PHY Reg: 0x135		Read: 0x0 
PHY Reg: 0x136		Read: 0x0 
PHY Reg: 0x137		Read: 0x0 
PHY Reg: 0x138		Read: 0x0 
PHY Reg: 0x139		Read: 0x0 
PHY Reg: 0x13a		Read: 0x0 
PHY Reg: 0x13b		Read: 0x0 
PHY Reg: 0x13c		Read: 0x0 
PHY Reg: 0x13d		Read: 0x0 
PHY Reg: 0x13e		Read: 0x0 
PHY Reg: 0x13f		Read: 0x0 
PHY Reg: 0x140		Read: 0x0 
PHY Reg: 0x141		Read: 0x0 
PHY Reg: 0x142		Read: 0x0 
PHY Reg: 0x143		Read: 0x0 
PHY Reg: 0x144		Read: 0x0 
PHY Reg: 0x145		Read: 0x0 
PHY Reg: 0x146		Read: 0x0 
PHY Reg: 0x147		Read: 0x0 
PHY Reg: 0x148		Read: 0x0 
PHY Reg: 0x149		Read: 0x0 
PHY Reg: 0x14a		Read: 0x0 
PHY Reg: 0x14b		Read: 0x0 
PHY Reg: 0x14c		Read: 0x0 
PHY Reg: 0x14d		Read: 0x0 
PHY Reg: 0x14e		Read: 0x0 
PHY Reg: 0x14f		Read: 0x0 
PHY Reg: 0x150		Read: 0x0 
PHY Reg: 0x151		Read: 0x0 
PHY Reg: 0x152		Read: 0x0 
PHY Reg: 0x153		Read: 0x0 
PHY Reg: 0x154		Read: 0x0 
PHY Reg: 0x155		Read: 0x0 
PHY Reg: 0x156		Read: 0x0 
PHY Reg: 0x157		Read: 0x0 
PHY Reg: 0x158		Read: 0x0 
PHY Reg: 0x159		Read: 0x0 
PHY Reg: 0x15a		Read: 0x0 
PHY Reg: 0x15b		Read: 0x0 
PHY Reg: 0x15c		Read: 0x0 
PHY Reg: 0x15d		Read: 0x0 
PHY Reg: 0x15e		Read: 0x0 
PHY Reg: 0x15f		Read: 0x0 
PHY Reg: 0x161		Read: 0xc 
PHY Reg: 0x16f		Read: 0x15 
PHY Reg: 0x170		Read: 0xc0d 
PHY Reg: 0x172		Read: 0x0 
PHY Reg: 0x180		Read: 0x752 
PHY Reg: 0x1a7		Read: 0x0 
PHY Reg: (MMD3_PCS_CTRL) 0x0		Read: 0x1140 

/* Re-reading some special registers once again */
PHY Reg: 0x0013		Read: 0x0 
 
PHY Reg: 0x0010		Read: 0x5848
 
PHY Reg: 0x0031 	Read: 0x10b0
 
PHY Reg: 0x0037 	Read: 0x2
 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0

  • 0 in reply to ABDULKERIM ALTUNTAS
    Prodigy 200 points

    Sorry, attached the incomplete file. The complete and updated register dump file should be DP83867_RegisterDump - e2e.txt

    Abdulkerim

    DP83867_RegisterDump - e2e.txt 
    Date: 02.03.2016

DP83867 SGMII Auto-Negotiation Timer Set to 2us
-----------------------------------------------

DP83867 100Mbps Half Duplex Case Register Dump
Note: SGMII link between C6678 and DP83867 is successfully established.

PHY Reg: 0x0		Read: 0x1140 
PHY Reg: 0x1		Read: 0x796d 
PHY Reg: 0x2		Read: 0x2000 
PHY Reg: 0x3		Read: 0xa231 
PHY Reg: 0x4		Read: 0x1e1 
PHY Reg: 0x5		Read: 0x4c81 
PHY Reg: 0x6		Read: 0x67 
PHY Reg: 0x7		Read: 0x2001 
PHY Reg: 0x8		Read: 0x0 
PHY Reg: 0x9		Read: 0x300 
PHY Reg: 0xa		Read: 0x0 
PHY Reg: 0xd		Read: 0x401f 
PHY Reg: 0xe		Read: 0x3800 
PHY Reg: 0xf		Read: 0x3000 
PHY Reg: 0x10		Read: 0x5848 
PHY Reg: 0x11		Read: 0x5f02 
PHY Reg: 0x12		Read: 0xffff 
PHY Reg: 0x13		Read: 0x1c40 
PHY Reg: 0x14		Read: 0x29c7 
PHY Reg: 0x15		Read: 0x0 
PHY Reg: 0x16		Read: 0x0 
PHY Reg: 0x17		Read: 0x40 
PHY Reg: 0x18		Read: 0x6150 
PHY Reg: 0x19		Read: 0x4444 
PHY Reg: 0x1a		Read: 0x2 
PHY Reg: 0x1e		Read: 0x2 
PHY Reg: 0x1f		Read: 0x0 
PHY Reg: 0x25		Read: 0x400 
PHY Reg: 0x31		Read: 0x10b0 
PHY Reg: 0x32		Read: 0xd3 
PHY Reg: 0x33		Read: 0x0 
PHY Reg: 0x37		Read: 0x3 
PHY Reg: 0x38		Read: 0x9801 
PHY Reg: 0x43		Read: 0x7a0 
PHY Reg: 0x6e		Read: 0x801 
PHY Reg: 0x6f		Read: 0x50 
PHY Reg: 0x71		Read: 0x0 
PHY Reg: 0x72		Read: 0x0 
PHY Reg: 0x86		Read: 0xd7 
PHY Reg: 0xd3		Read: 0x0 
PHY Reg: 0xdc		Read: 0x3800 
PHY Reg: 0xfe		Read: 0xe721 
PHY Reg: 0x134		Read: 0x1000 
PHY Reg: 0x135		Read: 0x0 
PHY Reg: 0x136		Read: 0x0 
PHY Reg: 0x137		Read: 0x0 
PHY Reg: 0x138		Read: 0x0 
PHY Reg: 0x139		Read: 0x0 
PHY Reg: 0x13a		Read: 0x0 
PHY Reg: 0x13b		Read: 0x0 
PHY Reg: 0x13c		Read: 0x0 
PHY Reg: 0x13d		Read: 0x0 
PHY Reg: 0x13e		Read: 0x0 
PHY Reg: 0x13f		Read: 0x0 
PHY Reg: 0x140		Read: 0x0 
PHY Reg: 0x141		Read: 0x0 
PHY Reg: 0x142		Read: 0x0 
PHY Reg: 0x143		Read: 0x0 
PHY Reg: 0x144		Read: 0x0 
PHY Reg: 0x145		Read: 0x0 
PHY Reg: 0x146		Read: 0x0 
PHY Reg: 0x147		Read: 0x0 
PHY Reg: 0x148		Read: 0x0 
PHY Reg: 0x149		Read: 0x0 
PHY Reg: 0x14a		Read: 0x0 
PHY Reg: 0x14b		Read: 0x0 
PHY Reg: 0x14c		Read: 0x0 
PHY Reg: 0x14d		Read: 0x0 
PHY Reg: 0x14e		Read: 0x0 
PHY Reg: 0x14f		Read: 0x0 
PHY Reg: 0x150		Read: 0x0 
PHY Reg: 0x151		Read: 0x0 
PHY Reg: 0x152		Read: 0x0 
PHY Reg: 0x153		Read: 0x0 
PHY Reg: 0x154		Read: 0x0 
PHY Reg: 0x155		Read: 0x0 
PHY Reg: 0x156		Read: 0x0 
PHY Reg: 0x157		Read: 0x0 
PHY Reg: 0x158		Read: 0x0 
PHY Reg: 0x159		Read: 0x0 
PHY Reg: 0x15a		Read: 0x0 
PHY Reg: 0x15b		Read: 0x0 
PHY Reg: 0x15c		Read: 0x0 
PHY Reg: 0x15d		Read: 0x0 
PHY Reg: 0x15e		Read: 0x0 
PHY Reg: 0x15f		Read: 0x0 
PHY Reg: 0x161		Read: 0xc 
PHY Reg: 0x16f		Read: 0x95 
PHY Reg: 0x170		Read: 0xc0d 
PHY Reg: 0x172		Read: 0x0 
PHY Reg: 0x180		Read: 0x752 
PHY Reg: 0x1a7		Read: 0xf020 
PHY Reg: (MMD3_PCS_CTRL) 0x0		Read: 0x1140 


/* Read some special registers once again */
PHY Reg: 0x0013		Read: 0x0 
Version register Exp: 0xa231 Read: 0xa231
 
Reg: 0x0010, Exp:0x5848 Read:5848
 
Reg: 0x0031, Read:10b0
 
Reg: 0x0037, Read:1
 
Reg: 0x0038, Read:9801
 
Reg: 0x00DC, Read:3800
 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

DP83867 100Mbps Full Duplex Case Register Dump
Note: No SGMII link between C6678 and DP83867 is established.

PHY Reg: 0x0		Read: 0x1140 
PHY Reg: 0x1		Read: 0x796d 
PHY Reg: 0x2		Read: 0x2000 
PHY Reg: 0x3		Read: 0xa231 
PHY Reg: 0x4		Read: 0x1e1 
PHY Reg: 0x5		Read: 0xcd81 
PHY Reg: 0x6		Read: 0x6f 
PHY Reg: 0x7		Read: 0x2001 
PHY Reg: 0x8		Read: 0x6001 
PHY Reg: 0x9		Read: 0x300 
PHY Reg: 0xa		Read: 0x0 
PHY Reg: 0xd		Read: 0x401f 
PHY Reg: 0xe		Read: 0x3800 
PHY Reg: 0xf		Read: 0x3000 
PHY Reg: 0x10		Read: 0x5848 
PHY Reg: 0x11		Read: 0x7f02 
PHY Reg: 0x12		Read: 0xffff 
PHY Reg: 0x13		Read: 0x1c40 
PHY Reg: 0x14		Read: 0x29c7 
PHY Reg: 0x15		Read: 0x0 
PHY Reg: 0x16		Read: 0x0 
PHY Reg: 0x17		Read: 0x40 
PHY Reg: 0x18		Read: 0x6150 
PHY Reg: 0x19		Read: 0x4444 
PHY Reg: 0x1a		Read: 0x2 
PHY Reg: 0x1e		Read: 0x2 
PHY Reg: 0x1f		Read: 0x0 
PHY Reg: 0x25		Read: 0x400 
PHY Reg: 0x31		Read: 0x10b0 
PHY Reg: 0x32		Read: 0xd3 
PHY Reg: 0x33		Read: 0x0 
PHY Reg: 0x37		Read: 0x2 
PHY Reg: 0x38		Read: 0x9801 
PHY Reg: 0x43		Read: 0x7a0 
PHY Reg: 0x6e		Read: 0x801 
PHY Reg: 0x6f		Read: 0x50 
PHY Reg: 0x71		Read: 0x0 
PHY Reg: 0x72		Read: 0x0 
PHY Reg: 0x86		Read: 0xd7 
PHY Reg: 0xd3		Read: 0x0 
PHY Reg: 0xdc		Read: 0x3800 
PHY Reg: 0xfe		Read: 0xe721 
PHY Reg: 0x134		Read: 0x1000 
PHY Reg: 0x135		Read: 0x0 
PHY Reg: 0x136		Read: 0x0 
PHY Reg: 0x137		Read: 0x0 
PHY Reg: 0x138		Read: 0x0 
PHY Reg: 0x139		Read: 0x0 
PHY Reg: 0x13a		Read: 0x0 
PHY Reg: 0x13b		Read: 0x0 
PHY Reg: 0x13c		Read: 0x0 
PHY Reg: 0x13d		Read: 0x0 
PHY Reg: 0x13e		Read: 0x0 
PHY Reg: 0x13f		Read: 0x0 
PHY Reg: 0x140		Read: 0x0 
PHY Reg: 0x141		Read: 0x0 
PHY Reg: 0x142		Read: 0x0 
PHY Reg: 0x143		Read: 0x0 
PHY Reg: 0x144		Read: 0x0 
PHY Reg: 0x145		Read: 0x0 
PHY Reg: 0x146		Read: 0x0 
PHY Reg: 0x147		Read: 0x0 
PHY Reg: 0x148		Read: 0x0 
PHY Reg: 0x149		Read: 0x0 
PHY Reg: 0x14a		Read: 0x0 
PHY Reg: 0x14b		Read: 0x0 
PHY Reg: 0x14c		Read: 0x0 
PHY Reg: 0x14d		Read: 0x0 
PHY Reg: 0x14e		Read: 0x0 
PHY Reg: 0x14f		Read: 0x0 
PHY Reg: 0x150		Read: 0x0 
PHY Reg: 0x151		Read: 0x0 
PHY Reg: 0x152		Read: 0x0 
PHY Reg: 0x153		Read: 0x0 
PHY Reg: 0x154		Read: 0x0 
PHY Reg: 0x155		Read: 0x0 
PHY Reg: 0x156		Read: 0x0 
PHY Reg: 0x157		Read: 0x0 
PHY Reg: 0x158		Read: 0x0 
PHY Reg: 0x159		Read: 0x0 
PHY Reg: 0x15a		Read: 0x0 
PHY Reg: 0x15b		Read: 0x0 
PHY Reg: 0x15c		Read: 0x0 
PHY Reg: 0x15d		Read: 0x0 
PHY Reg: 0x15e		Read: 0x0 
PHY Reg: 0x15f		Read: 0x0 
PHY Reg: 0x161		Read: 0xc 
PHY Reg: 0x16f		Read: 0x95 
PHY Reg: 0x170		Read: 0xc0d 
PHY Reg: 0x172		Read: 0x0 
PHY Reg: 0x180		Read: 0x752 
PHY Reg: 0x1a7		Read: 0x0 
PHY Reg: (MMD3_PCS_CTRL) 0x0		Read: 0x1140 

/* Read some special registers once again */
PHY Reg: 0x0013		Read: 0x0 
Version register Exp: 0xa231 Read: 0xa231
 
Reg: 0x0010, Exp:0x5848 Read:5848
 
Reg: 0x0031, Read:10b0
 
Reg: 0x0037, Read:2
 
Reg: 0x0038, Read:9801
 
Reg: 0x00DC, Read:3800
 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 



-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
++++++++++++++++++++++++++++++++++++++++++++++++++++
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

DP83867 SGMII Auto-Negotiation Timer Set to 800us
-------------------------------------------------

DP83867 100Mbps Half Duplex Case Register Dump
Note: SGMII link between C6678 and DP83867 is successfully established.

PHY Reg: 0x0		Read: 0x1140 
PHY Reg: 0x1		Read: 0x796d 
PHY Reg: 0x2		Read: 0x2000 
PHY Reg: 0x3		Read: 0xa231 
PHY Reg: 0x4		Read: 0x1e1 
PHY Reg: 0x5		Read: 0x4c81 
PHY Reg: 0x6		Read: 0x67 
PHY Reg: 0x7		Read: 0x2001 
PHY Reg: 0x8		Read: 0x0 
PHY Reg: 0x9		Read: 0x300 
PHY Reg: 0xa		Read: 0x0 
PHY Reg: 0xd		Read: 0x401f 
PHY Reg: 0xe		Read: 0x3800 
PHY Reg: 0xf		Read: 0x3000 
PHY Reg: 0x10		Read: 0x5848 
PHY Reg: 0x11		Read: 0x5f02 
PHY Reg: 0x12		Read: 0xffff 
PHY Reg: 0x13		Read: 0x1c40 
PHY Reg: 0x14		Read: 0x29c7 
PHY Reg: 0x15		Read: 0x0 
PHY Reg: 0x16		Read: 0x0 
PHY Reg: 0x17		Read: 0x40 
PHY Reg: 0x18		Read: 0x6150 
PHY Reg: 0x19		Read: 0x4444 
PHY Reg: 0x1a		Read: 0x2 
PHY Reg: 0x1e		Read: 0x2 
PHY Reg: 0x1f		Read: 0x0 
PHY Reg: 0x25		Read: 0x400 
PHY Reg: 0x31		Read: 0x10d0 
PHY Reg: 0x32		Read: 0xd3 
PHY Reg: 0x33		Read: 0x0 
PHY Reg: 0x37		Read: 0x3 
PHY Reg: 0x38		Read: 0x9801 
PHY Reg: 0x43		Read: 0x7a0 
PHY Reg: 0x6e		Read: 0x801 
PHY Reg: 0x6f		Read: 0x50 
PHY Reg: 0x71		Read: 0x0 
PHY Reg: 0x72		Read: 0x0 
PHY Reg: 0x86		Read: 0xd7 
PHY Reg: 0xd3		Read: 0x0 
PHY Reg: 0xdc		Read: 0x3800 
PHY Reg: 0xfe		Read: 0xe721 
PHY Reg: 0x134		Read: 0x1000 
PHY Reg: 0x135		Read: 0x0 
PHY Reg: 0x136		Read: 0x0 
PHY Reg: 0x137		Read: 0x0 
PHY Reg: 0x138		Read: 0x0 
PHY Reg: 0x139		Read: 0x0 
PHY Reg: 0x13a		Read: 0x0 
PHY Reg: 0x13b		Read: 0x0 
PHY Reg: 0x13c		Read: 0x0 
PHY Reg: 0x13d		Read: 0x0 
PHY Reg: 0x13e		Read: 0x0 
PHY Reg: 0x13f		Read: 0x0 
PHY Reg: 0x140		Read: 0x0 
PHY Reg: 0x141		Read: 0x0 
PHY Reg: 0x142		Read: 0x0 
PHY Reg: 0x143		Read: 0x0 
PHY Reg: 0x144		Read: 0x0 
PHY Reg: 0x145		Read: 0x0 
PHY Reg: 0x146		Read: 0x0 
PHY Reg: 0x147		Read: 0x0 
PHY Reg: 0x148		Read: 0x0 
PHY Reg: 0x149		Read: 0x0 
PHY Reg: 0x14a		Read: 0x0 
PHY Reg: 0x14b		Read: 0x0 
PHY Reg: 0x14c		Read: 0x0 
PHY Reg: 0x14d		Read: 0x0 
PHY Reg: 0x14e		Read: 0x0 
PHY Reg: 0x14f		Read: 0x0 
PHY Reg: 0x150		Read: 0x0 
PHY Reg: 0x151		Read: 0x0 
PHY Reg: 0x152		Read: 0x0 
PHY Reg: 0x153		Read: 0x0 
PHY Reg: 0x154		Read: 0x0 
PHY Reg: 0x155		Read: 0x0 
PHY Reg: 0x156		Read: 0x0 
PHY Reg: 0x157		Read: 0x0 
PHY Reg: 0x158		Read: 0x0 
PHY Reg: 0x159		Read: 0x0 
PHY Reg: 0x15a		Read: 0x0 
PHY Reg: 0x15b		Read: 0x0 
PHY Reg: 0x15c		Read: 0x0 
PHY Reg: 0x15d		Read: 0x0 
PHY Reg: 0x15e		Read: 0x0 
PHY Reg: 0x15f		Read: 0x0 
PHY Reg: 0x161		Read: 0xc 
PHY Reg: 0x16f		Read: 0x95 
PHY Reg: 0x170		Read: 0xc0d 
PHY Reg: 0x172		Read: 0x0 
PHY Reg: 0x180		Read: 0x752 
PHY Reg: 0x1a7		Read: 0xef20 
PHY Reg: (MMD3_PCS_CTRL) 0x0		Read: 0x1140

/* Read some special registers once again */
PHY Reg: 0x0013		Read: 0x0 
Version register Exp: 0xa231 Read: 0xa231
 
Reg: 0x0010, Exp:0x5848 Read:5848
 
Reg: 0x0031, Read:10d0
 
Reg: 0x0037, Read:1
 
Reg: 0x0038, Read:9801
 
Reg: 0x00DC, Read:3800
 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

DP83867 100Mbps Full Duplex Case Register Dump
Note: No SGMII link between C6678 and DP83867 is established.

PHY Reg: 0x0		Read: 0x1140 
PHY Reg: 0x1		Read: 0x796d 
PHY Reg: 0x2		Read: 0x2000 
PHY Reg: 0x3		Read: 0xa231 
PHY Reg: 0x4		Read: 0x1e1 
PHY Reg: 0x5		Read: 0xcd81 
PHY Reg: 0x6		Read: 0x6f 
PHY Reg: 0x7		Read: 0x2001 
PHY Reg: 0x8		Read: 0x6001 
PHY Reg: 0x9		Read: 0x300 
PHY Reg: 0xa		Read: 0x0 
PHY Reg: 0xd		Read: 0x401f 
PHY Reg: 0xe		Read: 0x3800 
PHY Reg: 0xf		Read: 0x3000 
PHY Reg: 0x10		Read: 0x5848 
PHY Reg: 0x11		Read: 0x7f02 
PHY Reg: 0x12		Read: 0xffff 
PHY Reg: 0x13		Read: 0x1c40 
PHY Reg: 0x14		Read: 0x29c7 
PHY Reg: 0x15		Read: 0x0 
PHY Reg: 0x16		Read: 0x0 
PHY Reg: 0x17		Read: 0x40 
PHY Reg: 0x18		Read: 0x6150 
PHY Reg: 0x19		Read: 0x4444 
PHY Reg: 0x1a		Read: 0x2 
PHY Reg: 0x1e		Read: 0x2 
PHY Reg: 0x1f		Read: 0x0 
PHY Reg: 0x25		Read: 0x400 
PHY Reg: 0x31		Read: 0x10d0 
PHY Reg: 0x32		Read: 0xd3 
PHY Reg: 0x33		Read: 0x0 
PHY Reg: 0x37		Read: 0x2 
PHY Reg: 0x38		Read: 0x9801 
PHY Reg: 0x43		Read: 0x7a0 
PHY Reg: 0x6e		Read: 0x801 
PHY Reg: 0x6f		Read: 0x50 
PHY Reg: 0x71		Read: 0x0 
PHY Reg: 0x72		Read: 0x0 
PHY Reg: 0x86		Read: 0xd7 
PHY Reg: 0xd3		Read: 0x0 
PHY Reg: 0xdc		Read: 0x3800 
PHY Reg: 0xfe		Read: 0xe721 
PHY Reg: 0x134		Read: 0x1000 
PHY Reg: 0x135		Read: 0x0 
PHY Reg: 0x136		Read: 0x0 
PHY Reg: 0x137		Read: 0x0 
PHY Reg: 0x138		Read: 0x0 
PHY Reg: 0x139		Read: 0x0 
PHY Reg: 0x13a		Read: 0x0 
PHY Reg: 0x13b		Read: 0x0 
PHY Reg: 0x13c		Read: 0x0 
PHY Reg: 0x13d		Read: 0x0 
PHY Reg: 0x13e		Read: 0x0 
PHY Reg: 0x13f		Read: 0x0 
PHY Reg: 0x140		Read: 0x0 
PHY Reg: 0x141		Read: 0x0 
PHY Reg: 0x142		Read: 0x0 
PHY Reg: 0x143		Read: 0x0 
PHY Reg: 0x144		Read: 0x0 
PHY Reg: 0x145		Read: 0x0 
PHY Reg: 0x146		Read: 0x0 
PHY Reg: 0x147		Read: 0x0 
PHY Reg: 0x148		Read: 0x0 
PHY Reg: 0x149		Read: 0x0 
PHY Reg: 0x14a		Read: 0x0 
PHY Reg: 0x14b		Read: 0x0 
PHY Reg: 0x14c		Read: 0x0 
PHY Reg: 0x14d		Read: 0x0 
PHY Reg: 0x14e		Read: 0x0 
PHY Reg: 0x14f		Read: 0x0 
PHY Reg: 0x150		Read: 0x0 
PHY Reg: 0x151		Read: 0x0 
PHY Reg: 0x152		Read: 0x0 
PHY Reg: 0x153		Read: 0x0 
PHY Reg: 0x154		Read: 0x0 
PHY Reg: 0x155		Read: 0x0 
PHY Reg: 0x156		Read: 0x0 
PHY Reg: 0x157		Read: 0x0 
PHY Reg: 0x158		Read: 0x0 
PHY Reg: 0x159		Read: 0x0 
PHY Reg: 0x15a		Read: 0x0 
PHY Reg: 0x15b		Read: 0x0 
PHY Reg: 0x15c		Read: 0x0 
PHY Reg: 0x15d		Read: 0x0 
PHY Reg: 0x15e		Read: 0x0 
PHY Reg: 0x15f		Read: 0x0 
PHY Reg: 0x161		Read: 0xc 
PHY Reg: 0x16f		Read: 0x95 
PHY Reg: 0x170		Read: 0xc0d 
PHY Reg: 0x172		Read: 0x0 
PHY Reg: 0x180		Read: 0x752 
PHY Reg: 0x1a7		Read: 0x0 
PHY Reg: (MMD3_PCS_CTRL) 0x0		Read: 0x1140 

/* Read some special registers once again */
PHY Reg: 0x0013		Read: 0x0 
Version register Exp: 0xa231 Read: 0xa231
 
Reg: 0x0010, Exp:0x5848 Read:5848
 
Reg: 0x0031, Read:10d0
 
Reg: 0x0037, Read:2
 
Reg: 0x0038, Read:9801
 
Reg: 0x00DC, Read:3800
 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0 
PHY Reg: 0x0013		Read: 0x0

  • 0 in reply to ABDULKERIM ALTUNTAS
    TI__Mastermind 19780 points
    Hi Abdulkerim,

    I want to post here that the solution consisted of setting RX_CTRL strap to mode 3 due to issue between link partner and DP83867 on cable side causing SGMII to not complete auto-negotiation process.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 200 points
    Hi Rob,

    Yes you are right. The issue has been solved by strapping RX_CTRL to Mode-3.

    Special thanks to you and your colleagues,

    Abdulkerim