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Camera link / Channel Link 1 Fanout

ADAM ROTHROCK
Prodigy 110 points
Other Parts Discussed in Thread: DS90CR288A, DS90CR287, DS25CP104A

I'm using the DS90CR288A to deserialize camera link video for a third party processor.  I also want to buffer the camera link so it can be simultaneously sent to an external frame grabber.

It's important to note that I can't change anything on the serialization end.

Ideally I would use a fanout buffer to duplicate the (five) LVDS signals.  One would go to the deserializer/video processor.  The other copy of camera link would got to an external connector.  I've haven't been able to find 5 channel fanout buffer for doing this. I'm fairly sure using multiple buffer ICs would introduce too much skew between the camera link pairs.

The other option I am reluctantly considering involves reserializing the video (after the channel link receiver) using the DS90CR287.

I'm looking for a simple, robust fanout solution--but I'm not really finding anything.  Any ideas?

  • 0
    TI__Expert 3050 points

    Hi Adam,

    What will be the clock rate of this link? How many chipsets or DS90CR287 devices do you plan to use for this one link?

    There are a couple of option that we can explore:

    1. Use multiple fanout devices to accommodate the 5 to 10 split of the LVDS lines
    2. Do the fanout in the parallel domain and re-serialize
    3. Convert to the Channel Link II serial format for easy 1:2 split

    Mike Wolfe

    DPS APPS / SVA

  • 0 in reply to Mike Wolfe
    Prodigy 110 points
    Hi Mike,

    The parallel clock is 48MHz so that should equate to a channel link clock of 336MHz. I'm only using one DS90CR288A to deserialize camera link for my processor--I'm not sure what the camera uses to serialize.

    Suggestion 1 is appealing because it seems simplest to me. However I'm concerned about introducing skew between the LVDS signals. My understanding is that using multiple fanout ICs will cause non-uniform delay between pairs . What is the maximum input skew that can be tolerated by the DS90CR288A receiver? My hope was to find a 5 to 10 splitter in one device.

    Suggestion 2 seems like the best option. Will a parallel buffer be required?
  • 0 in reply to ADAM ROTHROCK
    TI__Mastermind 29655 points
    Hi Adam,

    We do have some 2x2 and 4x4 LVDS crosspoint switches that may be used as a fanout for the LVDS lines. However, since we would need at least 3 4x4 LVDS crosspoint switches, I agree that the skew between not only channels but also from part-to-part may be undesirable (I am seeing a maximum part-to-part skew of 200 ps for the DS25CP104A).

    I agree with you that Suggestion 2 is a simpler task to undertake, where you fanout the deserialized DS90CR288A output, then re-serialize later for your connector output. A parallel buffer will be needed only if the drive capacitance of the DS90CR288A is insufficient to drive both the processor parallel load and the DS90CR287 serializer (assuming you use this serializer for the external connector).

    According to the datasheet, Figure 8 shows the CMOS/TTL Output Load and Transition Times are assured for a load capacitance of 8 pF. From the DS90C385 IBIS model (this is based on the same silicon die as the DS90CR287), the TxIN pins have a silicon capacitance of approximately 5.9 pF. It is therefore possible that the combination of the TxIN pin with the processor input pin may necessitate the use of a parallel buffer if the combined total surpasses 8 pF.

    Thanks,

    Michael