• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Subscribers 32 subscribers
  • Views 3393 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867 100-BASETX Configuration

Nathan Rabenold
Intellectual 745 points

Hi-

I am looking to switch to the subject PHY on our newest designs.  Due signal count constraints, I can only run 2-pair Ethernet communication.  Up until this point, I have been using an MII PHY with a 100Base-TX interface (one receive and one transmit diff pair) at 100Mbps.

I am interested in keeping that configuration with the DP83867 PHY, which states that it supports 100Base-TX.  The datasheet is not clear and I don't have a lot of experience with Ethernet.  Would I only need the A and B differential pairs connected to do this (i.e., cable pins 1,2,3,6)?  The datasheet only discusses connection of all four pairs to the external CAT-5 cable, but my question is if I run it in 100Base-TX mode, am I correct that two of those pairs (C and D) are not used?

Thank you for your assistance,

Nate

  • 0
    TI__Mastermind 31600 points
    Nate,

    You are correct. When the DP83867 operates in 100Base-TX, it can operate with only channels A and B.

    You will want to make sure that the 1000Base-T full-duplex and half-duplex advertised auto-negotiation capabilities in the Configuration Register 1 (CFG1), Address 0x0009, are not configured. Otherwise, a 1000Base-T capable link partner could try to link in 1000Base-T.

    Patrick
  • 0 in reply to Patrick OFarrell
    Intellectual 745 points
    Thank you, Patrick!

    So what is raising this question for me is the desire to use the AM571x processor on two separate designs. One will support 100-BASE-TX and another 1000BASE-T. The goal was to use the same PHY and processor interface on both designs. Obviously, the clock and configuration registers would need to differ accordingly.

    Do you know if the PHY is capable of outputting 100BASE-TX while operating over the RGMII interface to the processor. Or does use of RGMII between the processor and PHY automatically lock us in to a truly gigabit (4-pair) interface on the port side?

    Thank you,
    Nate
  • 0 in reply to Nathan Rabenold
    TI__Mastermind 31600 points
    Nate,

    The DP83867 can operate in 1000Base-T, 100Base-TX, or 10Base-T with an RGMII connection to the MAC.

    Patrick
  • 0 in reply to Patrick OFarrell
    Intellectual 745 points
    Thank you. Are channels C and D okay to be left floating in the case that we only operate on two channels?

    Nate
  • 0 in reply to Nathan Rabenold
    TI__Mastermind 31600 points
    Yes. If you are operating in 100Base-TX, channels C and D will be unused and can be left unconnected.

    Patrick
  • 0 in reply to Patrick OFarrell
    Intellectual 745 points
    Patrick,

    One final question. When operating in 100Base-TX, which of A/B is transmit and which is receive? Does it matter? The datasheet simply states that they are transmit/receive signals, but from we are used to having a dedicated transmit pair and dedicated receive pair. Can you offer some insight into how the PHY will use the A and B outputs in this configuration?

    Thank you,
    Nate
  • 0 in reply to Nathan Rabenold
    TI__Mastermind 31600 points
    Nate,

    Historically, the transmit and receive pairs of the cable interface were explicitly defined. Typically, the 100Base-TX transmit pair would connect to pins 1 and 2 of the RJ-45 connector and the receive pair would connect to pins 3 and 6 of the RJ-45. As a result, to connect two like devices together, a crossover cable would be used.

    In the IEEE 802.3 specification, the cable interface is referred to as the Media Dependent Interface (MDI). The process for automatically configuring the transmit and receive pairs is known as Auto-MDIX. The X stands for crossover. As part of the Auto-Negotiation process, Auto-MDIX will swap the transmit and receive pairs so that a crossover cable is not required to complete the link.

    So to answer your original question, which of A/B is transmit and which is receive depends on the application, but if you are using Auto-MDIX, it probably doesn't matter. There is more detail on Auto-MDIX in the DP83867 datasheet, but the key register bits are in the PHYCR register (address 0x0010). The MDI_CROSSOVER bits in the PHYCR register allow you to configure automatic crossover or to configure the transmit and receive pairs explicitly.

    Patrick
  • 0 in reply to Patrick OFarrell
    Intellectual 745 points
    Thanks, Patrick.

    I understand the MDI interface is application-specific. My question was with regard to the PHY itself; do the A and B channels need to correspond explicitly to Rx or Tx? From your answer and the datasheet, it sounds like auto-negotiation will configure the PHY channels appropriately based on how the MDI is configured (which for us is typically standard Ethernet cable to a PC). Is there a default configuration (as far as Rx or Tx for A/B channels)?

    Thanks for all your help,
    Nate
  • 0 in reply to Nathan Rabenold
    TI__Mastermind 31600 points
    Nate,

    Depending on which DP83867 derivative you are using, the default may depend on straps. Specifically which device are you targeting for your design?

    Patrick
  • 0 in reply to Nathan Rabenold
    TI__Mastermind 31600 points
    In that case, Auto-MDIX will be enabled by default. You can disable it by register access and, if you choose to do so, you can force the state of the transmit and receive pins using the manual MDI / MDIX configuration bit.

    Patrick