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TLK10232: [TLK10232] Questions regarding MDIO

Takashi Onawa
Genius 13200 points
Part Number: TLK10232

Hi Team,

My customer has 2 questions regarding MIDO, could you follow these questions below?

1. Pull-up registers

2.2kohm pull-up register are used on MDIO line though, can they change it to 1kohm?

According to My customer, They have seen bad waveform like below at MDIO lines (TLK10232 to FPGA) on their board. It looks like low pass filter was applied(There may be a relatively large parasitic capacitance on the lines).

 

2. Meaning of Tvalid indicated in 9.10 MDIO Timing Requirements

My customer want to know  what Tvalid means, could you tell me that with a timing chart like Figure 9-4. MDIO Read/Write Timing?

Regards,

Takashi Onawa

  • 0
    TI__Genius 16150 points

    Hello Takashi,

    How is the MDIO pin of the FPGA configured, and does anything else share the MDIO bus?  Typically MDIO is an open-drain I/O, meaning that when it is configured as an output it will either sink current to ground to pull the line low or be high impedance so that the line can be pulled high externally.  

    Could customer try a ~4.99k pull-up resistor? Even the MDIO specification mentions a pull-up resistor from 1.5K - 10K. In the TLK10232EVM you can find a ~4.02k pull-up resistor populated.

    Regarding the Tvalid:

    Regards,

    Luis Omar Moran

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    TI__Genius 13200 points

    Hi Luis-san,

    The MDIO line from FPGA is connected to two TLK10232 through connector and 4~5 inch PCB trace. 2.2kohm resister is populated as Pull-up resister on the line. I'm guessing that this is due to parasitic capacitance on MDIO line, and they also estimated that. Anyway, I recommend them to use more slower MDC rate to avoid this issue and they closed this issue ones.

    Regarding the Tvalid, Could you tell me the meaning of Tvalid in detail?
    I and my customer could not understand the meaning of the Tvalid you showed above. 

    Also, I and the customer think the Tvalid is defined as MDC down edge to MDIO transaction as below though, Is it really from up edge?

    If it was really from up edge, we could not secure its hold time in data read/write transaction in some cases.
    If Tvalid means TLK10232's output timing variation on MDIO line, it makes sense for us...

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 16150 points

    Hello Takashi-san,

    Sorry for the confusion. The Tvalid is as follows:

    Best Regards,

    Luis

  • 0 in reply to Luis Omar Moran
    TI__Genius 13200 points

    OK, simple question.

    "Tvalid" and "MDIO (output) delay time" shown in the figure below are same parameter, aren't they?  

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 13200 points
    Hi Luis-san,

    This thread has still been opening and I got a remainder on this from my customer.

    They want to know TLK10232's "TI" shown in the figure above to fix MIDO read timing. Could you ask the parameter to designer ASAP if the Tvalid and T1 is not same meaning?

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Genius 16150 points

    Hi Takashi-san,

    T1 is not the same parameter than Tvalid, basically the Tvalid is the time from MDC (rise) to MDIO valid (once the signal is hold low or high). Tvalid has a maximum of 40ns to be compliant with the MDIO communication.

    Thanks,

    Luis