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DS90UB929-Q1: Write EDID data from MCU to the serializer(DS90UB929-Q1) , but the EDID data is no effective, and serializer uses the default EDID data

Part Number: DS90UB929-Q1
Other Parts Discussed in Thread: DS90UB924-Q1

Hello,

current situation:  We have designed a PCBA with a serializer(ds90ub929-q1) ,  and it's connected to another board  with a deserializer(ds90ub924-q1) by LVDS. In the PCBA, we have a MCU which connected to serializer by I2C, after power on, the serializer uses the internal default EDID data, the screen resolution is error(1280*720). In order to achieve the correct resolution display(1280*768), we write EDID data from MCU to seriaiizer, and can receive every byte of the ACK, but the screen resolution is same as when didn't write EDID data.  So I think the EDID data is not effective. 

•question: What can I do to make serializer EDID data which writed from MCU valid and display the correct resolution picture? Before or after writing EDID data, which register and GPIO I need to set. Please help me, thanks.

comment: The EDID data is verified, no problem.when write EDID data,  the device address is 0x18, the register address is 0xA0.  We can successfully modify the values of other registers in serializer.

  • Hi,

    if you use 1280x768, it is NOT default resolution. You can select the EDID setting based on Ux929 which can support 4 kinds of EDID configurations. If you want to write assigned EDID to UB949 internal SRAM, you can use both EDID_SEL & REM_EDID_LOAD in mode_sel0/1 ( can use either strap or register setting) to choose the EDID from internal SDRAM, in this way, your HDMI source can read this assigned EDID through DDC. Detailed solution as below:

    The address registers provide the byte offset to the EDID SRAM.  When accessing EDID SRAM, only the APB_DATA0 register is used since the interface is 8-bits, and the APB_SELECT bits should be set to a value of 01 to select EDID SRAM.

     

    The process for reading EDID SRAM is as follows:

    1.  Write to APB_ADR0 to set the 8-bit register address.

    2.  Set the APB_READ bit in the APB_CTL register.  This will initiate the APB Interface read. 

        The APB_ENABLE bit must also be set during the APB_CTL register write, while the APB_SELECT bits must be set to 01.  If desired, the APB_AUTO_INC bit may be set to enable the auto-increment function.

    3.  Read the APB_DATA0 registers.

    4.  If APB_AUTO_INC was set, the next register location may be read by repeating steps 2 and 3, otherwise repeat steps 1-3 to read another register location.

    The process for writing the EDID SRAM is as follows:

    1.  Set APB_ENABLE in the APB_CTL register.  This bit should remain set through remainder of procedure.  The APB_SELECT bits should be set to 01.  If desired, the APB_AUTO_INC bit may be set to enable the auto-increment function.

    2.  Write to APB_ADR0 to set the 8-bit register address.

    3.  Write the 8-bit data to the APB_DATA0 register.  The APB Interface write will occur once APB_DATA0 has been written.

    4.  If APB_AUTO_INC is set, the next register location may be written by repeating step 2, otherwise repeat steps 1 and 2 to write another register location.

    You can verify whether you can read/write the correct data into EDID SDRAM,

    best regards

    Steven 

     

  • Hi,
    Thank you for your support, I try to write EDID data to the serializer UB929 according to the solution you provided, and EDID data read from serializer is the same as EDID data I write, but the screen does't display the picture. Before writing the EDID data, the register is set as following:

    register Address (0x4F) = data (0x00)
    register Address (0x54) = data (0x00)
    register Address (0x48) = data (0x0D)
    register Address (0x51) = data (0xA0)
    register Address (0x49) = data (0xA0)
    write EDID
    read EDID is OK

    or
    register Address (0x4F) = data (0x00)
    register Address (0x54) = data (0x00)
    register Address (0x48) = data (0x0D)
    register Address (0x49) = data (0xA0)
    write EDID
    read EDID is OK

    and so on

    I think if there are any registers that are not set up. please help me to check it, if possible, give me a solution as I wrote above.
  • Hi, what is the mode setting? can you review this setting? thanks.

    best regards,
    Steven
  • Hi:
    mode setting as follow:
    EDID_SEL(Display ID Select): 0;
    EXT_CTL(External Controller Override):0;
    REM_EDID_LOAD(Remote EDID Load):0;

    Is this current?
  • what is the reg values of 0x4F and 0x54?
    the setting of EDID_SEL / EXT_CTL and REM_EDID seem correct. what is the result for this setting?

    best regards,
    Steven
  • register Address (0x4F) = data (0x00)
    register Address (0x54) = data (0x00)

    please check my reply in Apr 27, 2018 8:30 AM
  • You can dump all the registers of UB949 for further analysis.

    Steven
  • register Address (0x4F) = data (0x00)
    register Address (0x54) = data (0x00)
    register Address (0x48) = data (0x0D)
    register Address (0x49) = data (0xA0)

    /*write EDID*/

    for(i=0;i<EDID_SIZE;i++)

    {

    register Address (0x4B) = EDID_buf[i]

    }

  • I need get the register values for UB949 when you have such issue. do you try whether your link can work at TI's default EDID (you can change the PC output resolution)?
    btw, what is the EDID for resolution? TI's default EDID code is preprogrammed in d/s page 19.
  • If you still have issues, you should isolate the issue step by step.
    1. is it the HDMI I/f issue? please check HDMI status register in UB929 d/s, such as 0X0C, 0x50, 0x5F, etc., we can check whether HDMI I/f is workable between your computer and UB929 EVM board. also, the EDID inputted is correct or not?
    2. if HDMI module inside chip can run well, then you can check the link between UB929 and de-serliaizer, you can use data pattern gen. to check this link.

    Any concern, please let me know.

    best regards
    Steven
  • Thank you for your support, I has resolved the issue, the solution is that I add 1s delay before setting registers.