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Original question:

PCA9548A: Understanding functionality of PCA9548A

PCA9548A: Understanding functionality of PCA9548A

Jerome Crocco
Prodigy 30 points
Part Number: PCA9548A

Hello,

 ZC702 Board.  I have a script to generate test images for VGA output (hsync, vsync, data, etc).  This part works and has been verified on VGA display.

I am trying to use the ZC702 board for an HDMI output for a first step of the project, However some issues with I2C and configuring device.  I could provide my I2C Controller and Config files.  Also the simulation files if someone is willing to take a look.  Really not clear to my why this is not working.  I have followed Application note AN-1270 from Analog Devices with the I2C writes.

 Some questions Follow:

Why does ZC702 documentation have 9 addresses for an 8 switch device?:  I2C Address is 0x74 but there is listed 8 other channels for each other device.

PCA9548 docs have another set of addresses for writing to PCA9548 I2C (Table 1 section 9.6 of documentation, 8 channels 0x70-0x77)  In this documentation 0x74 is channel 5.  

Should my aknowledge cycle be 1'b1 or 1'bz on the SDA line? I see some conflicting information here. 

Is clock stretching OK?  as you can see in my snippet there is some delay in the CLK while waiting for acknowledge.

In PCA documentation it states i need to provide Slave Address + Control Register.  Is this correct?  If I only have a single device on the SDA line, and i send 0000001 or 1111111 would there be effectively any difference. I understand the control register is to access different devices on the I2C channel.  If I only have a single device on a channel then enabling all of the devices or one of the devices should not make a difference?

Thanks

Jerome

 

Thanks,

  • 0
    TI__Guru 60850 points

    Hey Jerome,

    "Why does ZC702 documentation have 9 addresses for an 8 switch device?"
    -I am unsure why there are 9 addresses in your ZC702 documentation. Can you reference where you see that in the user guide?

    I assume you are talking about table 1-19 in the xilinx user guide for zc702. If that is the case, only one of our PCA9548A devices are used as it looks like there are other devices (8 others totaling 9 with ours).

    "I2C Address is 0x74 but there is listed 8 other channels for each other device."
    -Our device can be configured to have different addresses depending on how you arrange the hardware. (You do this by pulling high or low on the address pins to change the device's address). Multiple addresses are necessary to avoid address conflicts. I assume what you are referencing is actually just different devices with different I2C addresses and not channels of our device.

    "Should my aknowledge cycle be 1'b1 or 1'bz on the SDA line? I see some conflicting information here. "
    Acknowledge occurs every 9th clock cycle and should be zero for an ACK and 1 for a NACK. If you are trying to end a read sequence then need to NACK but if you are trying to write or continue a read then you need to ACK. It also depends who is ACKing, if you send 0x74h and a read/write bit then the master should not ack as the slave is the one who is acking and the master should be looking for it.


    "Is clock stretching OK? as you can see in my snippet there is some delay in the CLK while waiting for acknowledge."
    -I am not able to see your snippet, can you repost it? You need to click on the blue link that says "insert code,attach files,and more...." then click on the icon in the box above with the picture of an image. (copy pasting does not work sadly....)
    -In general clock stretching is okay through our switch and some delay is possible due to the propagation delay that switches introduce. I should also note that if you are talking directly to the PCA9548A then you should not do clock stretching.

    "In PCA documentation it states i need to provide Slave Address + Control Register. Is this correct?"
    Yes, you need to send the 7 bit address (0x74h it looks like in your case) after you you see the slave ACK you can then send the control register data.

    "If I only have a single device on a channel then enabling all of the devices or one of the devices should not make a difference?"
    You will not see a difference so long as the other channels have a pull up resistor. If they are floating it could be possible that the channels could float to GND and pulls the signals low for a short amount of time though this is VERY unlikely.

    Thanks,
    -Bobby

    Also if you have any other questions or are running into issues let me know. (Also attach scope shots if you do have issues)

  • 0 in reply to BOBBY
    Prodigy 30 points

    Thanks,.

    I am trying to write I2C to AnalogDevices AD7511 HDMI Chip so that it can be configured for subsequent output following AN-1270 (see last page)

    If I understand you correctly:

    From FPGA I should be sending 8bit HDMI Address from ZC702 documentation (0b0111001+ 0 to write)  + control register (1111111 + 0 to write) + 24bit from AN-1270 with specified writes.

    I2C for :  01110010; 11111111; 01110010; 0000001;0000000, where i have kept the SDA low for ACK, but I do have some clock stretching going on at the ACK. This is accceptable?

    The Master I2C_SDAT should be 1'b1 or 1'bz when waiting for ACK in 9th clock cycle?  I realize that the output will be a low coming from slave.

    It is acceptable sending control register as 11111111? 

    You would like to see no stretching of clock cycles i understand?  This will cause the device to not work?

    I wanted to ask of alternative ways to confirm receipt of ACK from slave besides using a logic analyzer.  For example, is it common practice to make a logical  condition which keeps the I2C_SCLK high until the SDAT is pulled low?  If i release the I2C_SDAT as above (by setting to 1'bz) the default state would be pulled high the  pull up resistor.  So therefore I should hold I2C_SCLK high until this line transitions to low (from the ACK coming from slave).

    Thanks,

    AN-1270.pdf

  • 0 in reply to Jerome Crocco
    TI__Guru 60850 points

    Hey Jerome,

    "From FPGA I should be sending 8bit HDMI Address from ZC702 documentation (0b0111001+ 0 to write)  + control register (1111111 + 0 to write) + 24bit from AN-1270 with specified writes."

    -The second step involving the control register is wrong. Should be:

    (11111111+ 0 to write) (notice I added an additional 1 because we want to write 8 bits into the control register)

    The + 0 is not supposed to be there because that is the 0th clock cycle where the slave is expected to ACK. In your previous data you've already indicated to the device you are going to write. (remember all data is in sequences of 8 and the last bit is for the transceiver to ACK/NACK)

    "+ 24bit from AN-1270 with specified writes."

    After you have sent the address and the channels you want to write to, you need to release the I2C bus (stop condition) and then initialize a start condition or perform a restart condition. This is required if you want to do something else besides continue writing to the control register otherwise the switch will still think you are trying to talk to it.

    So after writing to the switch, you need to (stop then start) then send the 7 bit address of the AD7511 and a read or write bit. (I assume you are writing) Then send your 24 bits (8 at a time and look for an ACK after the 9th clock cycle before sending the next 8). After that you need to release the I2C lines.

    In your waveform, I do not see any ACKs as it looks like the 9th clock pulse is just holding low and never going back up until a restart condition occurs?????

    "The Master I2C_SDAT should be 1'b1 or 1'bz when waiting for ACK in 9th clock cycle?  I realize that the output will be a low coming from slave."

    I am assuming your master is not capable of pulling high, (push pull architecture will damage the devices). I am not sure what 1'b1 or 1'bz is as this looks like a software question about your specific driver. I assume it should be 1 because you do not want to pull the line low but this looks like you are looking at bit1 which is not the ACK bit??? (No idea about this driver/code)

    "It is acceptable sending control register as 11111111? "

    Yes.

    "You would like to see no stretching of clock cycles i understand?  This will cause the device to not work?"

    Our device does not support directly seeing a clock stretch (you can clock stretch through the channels but not directly talking to our device). There is no need to clock stretch. I should mention that the master usually never does clock stretching, clock stretching is done by the slave device in order to have more time to parse data. The master should not clock stretch at all for what you are doing.

    "For example, is it common practice to make a logical condition which keeps the I2C_SCLK high until the SDAT is pulled low?"

    This is not possible with I2C because it is open drain. This means you can not actively pull the signal high. (If you do you will damage the pull down FETs when a low occurs). The master should be in a tri state mode if it is not pulling low.

    "If i release the I2C_SDAT as above (by setting to 1'bz) the default state would be pulled high the  pull up resistor."

    This is exactly what we want.

    "So therefore I should hold I2C_SCLK high until this line transitions to low (from the ACK coming from slave)."

    The master is the one that generates the clock signal, not the slave, you should continue to generate clock pulses (master shoudl generate the 9th clock pulse) but slave should be pulling SDA low on pulse 9.

    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    Do you have access to an o-scope and can you probe SDA/SCL during the first two communications? (when you send the slave address and the control register)

    A logic analyzer does not show me what the device is actually seeing and is easier for me to understand what is going on.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    Prodigy 30 points

    I have implemented what you said.  Please confirm.

    1)  below is look up table. First I write to PCA9548 @ 0x74.  I send 0xFF 3 times.  I dont think this makes a difference and allows me to use one LUT for config.

    2)  After I config all channels open, I then write to the ADV7511 at 0111001 and i add 1 for write.  followed by 24bits of data.

    Below is a link of simulation.  MI2C ACK and END are for state machine.  The key lines I think are the I2C_SDAT and I2C_SCLK which I think comply with standard.

    I

    Here is writing the first line:  8'b11101001,8hFF,8hFF,8hFF

    I will keep troubleshooting because ADV7511 is not working.  But this may be more downstream.  Please let me know if there are any errors writing to your device using this approach i have tried to repeat back to you.

  • 0 in reply to Jerome Crocco
    TI__Guru 62920 points
    Hi Jerome,

    Have you had any luck with the debug so far? Bobby is out of the office at the moment, but I saw that we never got back to you on your last post and so I took a look. I don't think I understand your SDA waveform for writing to the PCA9548A, though. After the start condition (when SDA goes low with SCL held high) I'd expect to see the device address (beginning with 1110), but it looks like the SDA line remains low for several clock cycles. Do you know why this is? I also don't see the device acknowledging the writes of FF (there should be a low bit driven by the slave node after each byte of data transfer). Do you know why this is? Some of the previous waveforms you provided seemed to match closer to what I would expect.

    Max