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DS90UB953-Q1: Data Voltage Variations

Antonio Fadhel
Genius 9410 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: DS90UB954-Q1,

Hi Team,

My customer is having issues communicating between the '943 serializer and '954 deserializer. When they monitor the the CSI-2 data coming into the '953 with a scope, the high speed section of the data alternates between roughly 500mV and 210mV pk-pk (see below image). When they hold the PDB input of the chip to ground the issue does not happen, high speed data is consistently just below 500mv pk-pk. They suspect that the terminations to the DPHY in the part are somehow changing. Any ideas what could be causing this?

Thanks,

Antonio

  • 0
    TI__Genius 11340 points

    Hi Antonio,

    It is likely that you don't have proper termination. Could you check other CSI-2 lanes to see if they are also having the same issue?

    In High-Speed mode, you should be seeing ~200mV swing. Could you check your protocol to make sure that the sequence to enter HS mode is the following: LP-11, LP-01, LP-00 with correct timing (shown below)?

    As a debug step, you could force termination on the 953 by changing the values on register 0x24.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    TI__Genius 9410 points
    Thanks, Jiashow. The customer was able to get past this issue, but are still trying to get their application to work correctly. They requested the following app note referenced on the datasheet: SNLA267 “How to Design a FPD-Link III SystemUning DS90UB953 and DS90UB954”. Can you please provide it? I can't find it anywhere.
  • 0 in reply to Antonio Fadhel
    TI__Genius 11340 points

    Hi Antonio,

    The app note is not yet published as there are some minor changes we need to fix before publication.

    You could refer to the user guides for the DS90UB953-Q1 and DS90UB954-Q1 for general guidance on bringing up the system.

    You can also reference the training videos 953-954 System Design and Operation.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    TI__Genius 9410 points
    Hi Jiashow,

    Thanks - I have shared those in the past but was hoping the app note was available. Also, they are generating a RAW10 test pattern but are converting it to a CSI-2 data stream in their FPGAs in order to send it to the 953. Should they configure the 953 and 954 as CSI-2 or RAW10 mode?

    Thanks,
    Antonio
  • 0 in reply to Antonio Fadhel
    TI__Genius 11340 points
    Hi Antonio,

    You would configure the SerDes as CSI-2 mode.

    Best,
    Jiashow