SN65DP159: SN65DP159RSB Test issue

The default mode of SN65DP159 is HDMI1.4. To work at HDMI2.0, either by I2C 0r by DDC training though EDID.
For DDC training, the SNx5DP159 snoops data rate information to determine the TMDS clock ratio and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is 1/40 of TMDS bit period. If a 0 is written, then the TMDS clock is 1/10 of TMDS bit period. The SNx5DP159 will always default to 1/10 of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1.
in schematic, you may need you add pullup resistors on DDC pins.

Hi Brain,

Thanks for your response. As you can see from the schematic, customer is using DP159 under pin strap mode. According to the suggestion in the datasheet, in order to past the SI test at HDMI2.0, below pins needed to be set accordingly:

For the SNx5DP159RSB:

Pin Strapping HDMI2.0 and HDMI1.4b

Vsadj Resistor = 6.5 kΩ

PRE_SEL = L for –2 dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

But after the correct pin settings, the test equipment still shows the DR at HDMI1.4.

My question is that, after the above pin settings,

1. If the video source outputs HDMI2.0 compatible DR, is there anything else needed to be configured for DP159?

2. Is DDC communication still needed to set the correct TMDS_CLOCK_RATIO_STATUS bit and to tell the video source to output HDMI2.0 compatible DR?

Thanks,

Andonis. 

even if video source outputs HDMI2.0, DDC communication is still needed to set the correct TMDS_CLOCK_RATIO_STATUS bit to make DP159 work in 2.0 mode