DS90UB935-Q1: Using CSI-2 non-synchronous CLK_IN mode in DVP mode

Hello Nao,

In the datasheet this is a general information that you can use the CSI-2 Non-Synch external clock mode with other (CSI-2) devices. But if using a Parallel deserializer then you can only use the DVP Mode.

Hi, Hamzeh

This means that we can not use CSI-2 Non-Synch external clock mode (010) with DVP mode, right?

Regards
Nao

Hello Nao,

DVP mode is a "Non-Synch External Clock mode" but special for DVP, not CSI-2.

What is the problem of using the DVP Mode? Why do you want to use the CSI-2 Non-Synch Mode?

Hello, Hamzeh

Sorry. I was misunderstanding the customer questions.

My customer's question is here.

Do we need to be synchronized to the Input data of CSI-2 applied to CLKIN when using DVP external clock mode?

We are planning the CLKIN clock makes from non sync external clock.

This clock is same frequency but irrelevant the CMOS sensor. Hence it does not synchronize to the Input frequency.

Regards,

Nao

Hello Nao,

is the customer using 935-936 as shown in the block diagram, or 935-934 as in the top of the thread?

Hi, Hamzeh

Our customer is using 935-934.

Regards,
Nao

Hi, Hamzeh

Do you have any update?

Regards,
Nao

Hi, Hamzeh

Thank you very much.
I will get back, if our customer has other questions.

Regards,
Nao

Hello, Hamzeh

Our customer is considering the following clock diagrams.

DS90UB935 setting is here.
- HS_CLK_DIV:0x21
- DIV_M_VAL:0x01(defult)
- DIV_N_VAL: 0x1C

==== Clock Setting ====
- CLKIN is 48MHz
- HS_CLK_DIV is Div by 2
- M is 1
- N is 28
- CLKOUT = 48MHz*28/2*(1/28) = 24MHz
===================

Q. Are their OK to the using DVP external clock mode with this synchronous clock?

Regards,
Nao

Hi, Hamzeh

Are there any problems with these registor settings?

Regards,

Nao

Yes, the values are correct.
0x06=0x21
0x07=0x1C

Hello, Hamzeh

Thank you for your reply. I have one more question.
I missed the conditions of HS_CLK_DIV.

Do we need to change the register setting to following, if this condition is mandatory?

==== Clock Setting ====
- CLKIN is 48MHz
- HS_CLK_DIV is Div by 4
- M is 1
- N is 14
- CLKOUT = 48MHz*28/4*(1/14) = 24MHz
===================

==== Register Setting ====
0x06=0x41
0x07=0x0E
===================

Could you tell me which one is correct?

Regards,
Nao

Hello Nao,

it is already set to "Div by 4" which means reg 0x06 = 0x21

So the register values should be:

0x06=0x21
0x07=0x1C

Hello, Hamzeh

UB935 datasheet said this register value is here.

I guess the default value of CLKOUT_CTRL0 (Address 0x06) is 0x41 not 0x21.
However, you said "it is already set to "Div by 4" which means reg 0x06 = 0x21".
Q1. Which one is correct value?

And the note of "Table 6. Clocking Modes" said that [(1) HS_CLK_DIV typically should be set to either 16, 8, or 4 (default)].

Q2. Can we set 0x21(Div by 2) to CLKOUT_CTRL0 (Address 0x06) on DVP mode?
My understanding of this annotation is we CAN'T set 0x21 (Div by 2) and 0x01 (Div by 1). Is my understanding correct?

Regards,
Nao

Hello Nao,

As I said, it is already set to "Div by 4" which means reg 0x06 = 0x21. Please note HS_CLK_DIV has the bits [7:5] not [7:4] that's why it is in the register description written 0x21 but it is 0x41 (01000001). Hope it is clear now?!

So the register values should be:

0x06=0x21
0x07=0x1C

Hello Hamzeh

Thank you for your reply.
I have a simple question.

What is the default value of CLKOUT_CTRL0 (Address 0x06)?

Regards,
Nao

Hello Nao,

The default value of the 0x06 = 0x41
The default value of the 0x07 = 0x28

I believe there is a misunderstanding issue here. Let me please repeat and correct me if I am wrong.

the customer want to have these settings, correct?
- CLKIN is 48MHz
- HS_CLK_DIV is Div by 4
- M is 1
- N is 14

Then the register settings should be:
0x06=0x41
0x07=0x0E

Sorry for the confusion!

Hello, Hamzeh

Our Customer wants to know the following register setting.
CLKIN is 48MHz
CLKOUT is 24MHz

Regards,
Nao

Hi, Hamzeh

Thanks. I can close this thread.

Regards,
Nao