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DS90UB947-Q1: Register 0x54 setting having effect on back-channel GPIO0 with DS90UB947-Q1 and DS90UB948-Q1

Alan O
Mastermind 32575 points
Part Number: DS90UB947-Q1
Other Parts Discussed in Thread: DS90UB948-Q1

My customer has been having issues with the DS90UB947-Q1 inability to pass GPIOs on the back channel; particularly GPIO0.  They claim the solution was to set Reg 0x54 of the 947 from its boot up value of 0x3 to 0x0.  They also said Reg 0x54 description table implies we would only have to clear bit 1, but in actuality we have to clear [1:0].  This is different than what the datasheet describes.  Can you please clarify this register table (especially "Reserved" bit 0), and how it is affects back-channel operation for GPIO0?  

Something they noticed in the beginning was register 0x28 of the DS90UB948-Q1 partner device.  The 948 register 0x28 was reading back 0x18, and this seems to indicate GPIO0 and GPIO1 are configured as alternative I2S output mode.  After writing 947 register 0x54 to 0x0, 948 register 0x28 was reading back 0x11 which means GPIO0 and GPIO1 are configured as normal operation.  Would 948 register 0x28[bit 7] = 0 explain how 947 register 0x54 affects GPIO0 and GPIO1 (since bit 7 enables forward channel control of 948 register 0x28)?

Regards,
Alan

  • 0
    TI__Guru** 103215 points

    Hello Alan,

    Can you please check your MODE pin strapping for 947? What divider is being used? Bit 0 of 0x54 is set from the MODE_SEL0 pin strapping. In mode 2 and 6 this value will default to "1" and must be set to 0 to pass GPIO through the back channel. 

    Best Regards,

    Casey

  • 0 in reply to Casey McCrea
    TI__Mastermind 32575 points

    Hi Casey,

    MODE_SEL0 has 40.2k pulldown only (Mode0 #1) and MODE_SEL1 has 90.9k pulldown and 113k pullup (Mode1 #4).  Register 0x13 (MODE_SELx decode) reads back with 0xB8, which matches the pin-strap setting.  Any other ideas on why Bit 0 does not default to "0"?

    Regards,
    Alan

  • 0 in reply to Alan O
    TI__Guru** 103215 points

    Hello Alan,

    Sorry I was mistaken in my above post. The MODE_SEL1 pin sets this bit in 0x54 and actually MODE_SEL1 settings of 2, 4, 6, or 8 cause this bit to go high. Apologies for the confusion. So for MODE_SEL1 = 4 then this is expected behavior. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Mastermind 32575 points

    Hi Casey,

    It seem the MODE_SEL1 table is missing a right-most column with alternating 0’s (for odd # modes) and 1’s (for even # modes) which maps to the initial value of Bit 0 of Register 0x54 - is this correct?    If so, could you please consider revising the datasheet (e.g. MODE_SEL1 table and Register 0x54 description table) to document the MODE_SEL1 pin strap effect on the back-channel GPIO functionality?

    Thanks,

    Alan

  • 0 in reply to Alan O
    TI__Guru** 103215 points

    Hello Alan,

    Yes we will add it to the next datasheet update. 

    Best Regards,

    Casey