Other Parts Discussed in Thread: DS90UB948-Q1
My customer has been having issues with the DS90UB947-Q1 inability to pass GPIOs on the back channel; particularly GPIO0. They claim the solution was to set Reg 0x54 of the 947 from its boot up value of 0x3 to 0x0. They also said Reg 0x54 description table implies we would only have to clear bit 1, but in actuality we have to clear [1:0]. This is different than what the datasheet describes. Can you please clarify this register table (especially "Reserved" bit 0), and how it is affects back-channel operation for GPIO0?
Something they noticed in the beginning was register 0x28 of the DS90UB948-Q1 partner device. The 948 register 0x28 was reading back 0x18, and this seems to indicate GPIO0 and GPIO1 are configured as alternative I2S output mode. After writing 947 register 0x54 to 0x0, 948 register 0x28 was reading back 0x11 which means GPIO0 and GPIO1 are configured as normal operation. Would 948 register 0x28[bit 7] = 0 explain how 947 register 0x54 affects GPIO0 and GPIO1 (since bit 7 enables forward channel control of 948 register 0x28)?
Regards,
Alan