TMDS171: TMDS171 : DDC- SCL_SRC -> SCL_SNK freqency change in source side application

Akihisa-san

The TMDS171 supports DDC clock stretching. Clock stretching, or clock synchronization, is used by a slave to notify the master to slow down the clock speed. The slave slows down the communication by stretching SCL, the clock line. Basically, during a SCL low phase, the slave holds down SCL to prevent it from rising again, enabling it to slow down the SCL clock rate or to stop the communication for a while. This situation may happen when the slave is waiting for its internal operation to complete.

The master, on the other hand, is required to read back the clock signal after releasing it to the high state and wait until the line has actually gone high.

Not all masters support DDC clock stretching. There is a note in Section 8.4.3 of the TMDS171 datasheet.

The TMDS171 utilizes clock stretching for DDC transactions. As there are sources and sinks that do not perform this function correctly as system may not work correctly as DDC transactions are incorrectly transmitted/recieved. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The TMDS171 will need its SDA_SNK and SCL_SNK pins connected to this link.

Thanks

David