• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 369 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI84: In test mode, there is a colorful column shown while untick the test mode, there is only green, red and black colors repeated.

Wenting Wu
Intellectual 2395 points
Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hello I.K, 

Sorry to bother you again. This post is followed up with the question which we've discussed in last week. I loop in my customers as well as their Qualcomm supports  to talk with you directly within this post. The Run Rate volume of SN65DSI84 is larger than 50Ku/Y for a urgent Bank tender project. Thanks for your supports in advance. Here are some questions from the customer:

1. The customers have input the right DSI file into DSI-TUNER. They still want to try burst mode and non-burst mode. They feedback that when they adjust the burst/ non-burst mode in DSI-TUNER, the related register doesn't change even under test mode. 

2. Should the BLLP EOF is in HS mode or LS mode? and should IN BLLP in HS mode or LS mode?

3. The line time of DSI signal from qualcomm should be keep the same with the output LVDS signal of SN65DSI84, should the DSI send horizantal and vertical signals? 

Hello Devin and Fei,

Please attach your other questions in this post if you have.

  • 0
    TI__Mastermind 35130 points

    Hi Wenting,

    1. Those are just informational settings for the DSI-Tuner - there is not a setting for burst / non-burst mode for the DSI84; it inherently accepts both modes.

    2. Not quite sure I understand the phrasing of this question, but please see Figure 17 in the datasheet (BLLP = NOP/LP).

    3. The DSI source needs to send horizontal/vertical sync signals, yes. The line time is the time between consecutive HSS signals, or from VSS to the first HSS signal. The line time on the DSI side should be the same as the line time on the LVDS side. You can calculate the line time using equations (4) and (5) in this application note: http://www.ti.com/lit/an/slla356/slla356.pdf For single DSI to dual LVDS, each LVDS channel should have the same line time as the DSI input. Alternatively, the DSI-Tuner calculates it in the "Output" window based on the settings entered. 

    Regards,

    I.K.