Part Number: DP83867IR
when dp83867irrgz realizes 100m communication, phy and PC end self negotiate successfully, but PC cannot Ping the IP address of the device
The hardware platform is the 7020 of the zynq7000 series of Xilinx. The dp83867irrgz (48pin) is connected with the PS terminal of the 7020.The requirement is to realize 100MHz network communication in rgmii mode only.
The schematic is as follows:
Strap pin only pin 38 (Rx_ CTRL) pull up the 5.76k resistor and pull down the 2.49k resistor to realize the automatic negotiation enable of Mode3, and other strap pins are open which in mode1
Through MDC and MDIO, the registers can be read and written normally. The register settings are as follows:
Read Register RegisterNum PhyDataRead Register RegisterNum PhyData[796D]Read Register RegisterNum PhyDataRead Register RegisterNum PhyData[A231]Read Register RegisterNum PhyData[0DE1]Read Register RegisterNum PhyData[CDE1]Read Register RegisterNum PhyData[006F]Read Register RegisterNum PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum[000A] PhyDataRead Register RegisterNum[000B] PhyDataRead Register RegisterNum[000C] PhyDataRead Register RegisterNum[000D] PhyData[401F]Read Register RegisterNum[000E] PhyData[00D3]Read Register RegisterNum[000F] PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum PhyData[6C02]Read Register RegisterNum PhyDataRead Register RegisterNum PhyData[9CC0]Read Register RegisterNum PhyData[29C7]Read Register RegisterNum PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum PhyDataRead Register RegisterNum[001A] PhyDataRead Register RegisterNum[001B] PhyDataRead Register RegisterNum[001C] PhyDataRead Register RegisterNum[001D] PhyDataRead Register RegisterNum[001E] PhyDataRead Register RegisterNum[001F] PhyDataRead Extended Register RegisterNum PhyData[10B0]Read Extended Register RegisterNum PhyData[00D0]Read Extended Register RegisterNum PhyDataRead Extended Register RegisterNum PhyData[07A0]Read Extended Register RegisterNum PhyDataRead Extended Register RegisterNum[006E] PhyData[000E]Read Extended Register RegisterNum[006F] PhyDataRead Extended Register RegisterNum PhyDataRead Extended Register RegisterNum PhyDataRead Extended Register RegisterNum PhyData[00A8]Read Extended Register RegisterNum[00E9] PhyData[9F22]Read Extended Register RegisterNum[00FE] PhyData[E721]
1. LED0 is on, indicating that the link is established; LED2 flashes intermittently, indicating that data has been received or sent
2. It can be seen from the "Networking" of the task manager at the connected PC that the PC can discover the connection with the 100MHz network device, which indicates that phy and the link partner can negotiate successfully
3、RX_ CLK outputs 25MHz clock signal, RX_CTRL will produce 8321ns high level intermittently, other time is low level, RD0 ~ RD3 can also be measured waveform
But GTX_ CLK has no signal generation, TX_ CTRL and tx0 ~ tx3 also maintain a certain level state. There is such a description in the manual, as shown in the underlined part below. But now GTX_ CLK has no clock signal.
Does it mean that MAC has not been at the same rate as PHY? Why not have the same rate? How can we achieve the same rate?
To sum up, the negotiation between phy and link partner is normal, but there seems to be no effective connection between phy and MAC. Because I am not familiar with 802.3 protocol, what kind of data frame should be between MAC and PHY? How to realize the communication between the two layers?
Best Regards, Amy Luo
The MAC should provide a TX_CLK matching the RX_CLK provided by the PHY. Is the zynq7000 MAC an FPGA implementation or dedicated MAC interface?
Can you also confirm if all FPGA pins connected to the PHY MAC interface have internal pull-up/pull-down states? Based on the SOR register 0x006E it appears the PHY ID of the device is 0xE, is that correct? Is this set through external strap resistors?
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In reply to Justin Lazaruk:
Thank you for your reply and make the following supplementary explanation for your asking:
1\FPGA and ARM are integrated in zynq7000. MAC is the dedicated MAC interface of ARM end, and the pin connected to PHY MAC interface is tri-state interface, as shown in the figure below
2、PHY_ ID is a little different from the theory. There is a little missing in the description of the problem. In fact, RXD0 (33pin) is the same as RX_Ctrl in pulling up 5.76k, pulling down 2.49k, and in Mode3, while RXD2 is open without pulling up / down. Theoretically, it should be PHYID3 = 0, PHYID2 = 0, PHYID1= 1, PHYID0 = 0. In fact, the voltage measured by RXD2 in the open state is 0.6V, and the PHY chip will judge it as Mode4, so the actual reading is PHYID3 = 1, PHYID2 = 1, PHYID1 = 1, PHYID0 = 0, and the value read in the register is 0x0e. Here, the measured voltage of RXD0 ~ RXD3 in open state is about 0.6V, is it a problem?
3. Another thing that I don't quite understand is the difference between GTX_CLK and TX_CLK. The 48pin dp83867irrgz I chose only has GTX_ CLK pin, while 64pin IRPAP has GTX_ CLK and TX_ CLK。 Is it GTX_ CLK is 1000M clock, while TX_ CLK is a 10 / 100M clock? My main control chip only supports the MAC interface of RGMII, and the MAC dedicated interface has only one TX_CLK. Does it mean that my main control chip can only connect with 48pin IRRGZ, but not 64pin IRPAP (because 64pin IRPAP needs GTX_ CLK and TX_ CLK）? The customer's current system is 100MHz communication under the RGMII interface. The customer would like to know if GTX_CLK is compatible with 10 / 100 / 1000MHz?
sorry，I am not familiar with Ethernet Phys. Please point out the unclear description.
In reply to Amy Luo:
2. Yes, I would say that the open state voltage on strap pins being 0.6V is problematic. This suggests there is some pull-up resistance provided by the MAC that is strapping the device into intermediate modes. Can you confirm only RXD[0:3] are affected by this?
3. The GTX_CLK is the RGMII clock provided from the MAC to the PHY in RGMII mode. This should match the RX_CLK frequency in RGMII mode. The TX_CLK in the 64pin device is the MII clock that is an output of the PHY in MII mode.
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