Hi team,
Problem Description:
when dp83867irrgz realizes 100m communication, phy and PC end self negotiate successfully, but PC cannot Ping the IP address of the device
The hardware platform is the 7020 of the zynq7000 series of Xilinx. The dp83867irrgz (48pin) is connected with the PS terminal of the 7020.The requirement is to realize 100MHz network communication in rgmii mode only.
The schematic is as follows:
Strap pin only pin 38 (Rx_ CTRL) pull up the 5.76k resistor and pull down the 2.49k resistor to realize the automatic negotiation enable of Mode3, and other strap pins are open which in mode1
Through MDC and MDIO, the registers can be read and written normally. The register settings are as follows:
Read Register RegisterNum[0000] PhyData[1140]
Read Register RegisterNum[0001] PhyData[796D]
Read Register RegisterNum[0002] PhyData[2000]
Read Register RegisterNum[0003] PhyData[A231]
Read Register RegisterNum[0004] PhyData[0DE1]
Read Register RegisterNum[0005] PhyData[CDE1]
Read Register RegisterNum[0006] PhyData[006F]
Read Register RegisterNum[0007] PhyData[2001]
Read Register RegisterNum[0008] PhyData[6001]
Read Register RegisterNum[0009] PhyData[0300]
Read Register RegisterNum[000A] PhyData[0800]
Read Register RegisterNum[000B] PhyData[0000]
Read Register RegisterNum[000C] PhyData[0000]
Read Register RegisterNum[000D] PhyData[401F]
Read Register RegisterNum[000E] PhyData[00D3]
Read Register RegisterNum[000F] PhyData[3000]
Read Register RegisterNum[0010] PhyData[1140]
Read Register RegisterNum[0011] PhyData[6C02]
Read Register RegisterNum[0012] PhyData[0000]
Read Register RegisterNum[0013] PhyData[9CC0]
Read Register RegisterNum[0014] PhyData[29C7]
Read Register RegisterNum[0015] PhyData[0000]
Read Register RegisterNum[0016] PhyData[0000]
Read Register RegisterNum[0017] PhyData[0040]
Read Register RegisterNum[0018] PhyData[6150]
Read Register RegisterNum[0019] PhyData[4444]
Read Register RegisterNum[001A] PhyData[0002]
Read Register RegisterNum[001B] PhyData[0000]
Read Register RegisterNum[001C] PhyData[0000]
Read Register RegisterNum[001D] PhyData[0000]
Read Register RegisterNum[001E] PhyData[0002]
Read Register RegisterNum[001F] PhyData[0000]
Read Extended Register RegisterNum[0031] PhyData[10B0]
Read Extended Register RegisterNum[0032] PhyData[00D0]
Read Extended Register RegisterNum[0033] PhyData[0000]
Read Extended Register RegisterNum[0043] PhyData[07A0]
Read Extended Register RegisterNum[0055] PhyData[0000]
Read Extended Register RegisterNum[006E] PhyData[000E]
Read Extended Register RegisterNum[006F] PhyData[0100]
Read Extended Register RegisterNum[0071] PhyData[0000]
Read Extended Register RegisterNum[0072] PhyData[0000]
Read Extended Register RegisterNum[0086] PhyData[00A8]
Read Extended Register RegisterNum[00E9] PhyData[9F22]
Read Extended Register RegisterNum[00FE] PhyData[E721]
Debugging results:
1. LED0 is on, indicating that the link is established; LED2 flashes intermittently, indicating that data has been received or sent
2. It can be seen from the "Networking" of the task manager at the connected PC that the PC can discover the connection with the 100MHz network device, which indicates that phy and the link partner can negotiate successfully
3、RX_ CLK outputs 25MHz clock signal, RX_CTRL will produce 8321ns high level intermittently, other time is low level, RD0 ~ RD3 can also be measured waveform
But GTX_ CLK has no signal generation, TX_ CTRL and tx0 ~ tx3 also maintain a certain level state. There is such a description in the manual, as shown in the underlined part below. But now GTX_ CLK has no clock signal.
Does it mean that MAC has not been at the same rate as PHY? Why not have the same rate? How can we achieve the same rate?
To sum up, the negotiation between phy and link partner is normal, but there seems to be no effective connection between phy and MAC. Because I am not familiar with 802.3 protocol, what kind of data frame should be between MAC and PHY? How to realize the communication between the two layers?