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DP83620: TD+/TD- and RD+/RD- pin status during power down

Part Number: DP83620
Other Parts Discussed in Thread: TS3L4892,

Hi Sir/Madam,

What will be the status of the TD+/TD- and RD+/RD- pins during power off condition? We are using the two DP83620 part along with the TS3L4892 switch for Pass through function (connecting two RJ45 port or connecting the each RJ45 port with its respective Ethernet PHY).

The TS3L4892 switch will be in on condition when the DP83620 is in off condition to enable pass through function. During this condition the Switch will be configured by default to connect the two RJ45 ports together disconnecting the Ethernet Phy from RJ45 ports. We want ensure in this condition there is no current flow from TS3L4892 to DP83620 which can damage the Ethernet PHY. Will the TD+/TD- and RD+/RD- pins be in High Impedance state during off condition.

Regards,

M Amarnath

  • I would also like to know what will be the Maximum allowable current through the TD+/TD- and RD+/RD- pins for DP83620

  • Hello M Amarnath,

    I will need a couple of days to investigate this matter. I expect to have a response by EoD Thursday.

    Sincerely,

    Gerome

  • Hello M Amarnath,

    This application is not a general use case, as in most of our boards, the MDI pins are terminated with 49.9 Ohm resistors to 3.3V and are magnetically isolated from the rest of the system. 

    I would ask you to try this measurement out using loose (not soldered on board) samples of the DP83620 device. By taking an ohmmeter and directly measuring the resistance between the MDI pins (13, 14, 16, 17) and GND, you can determine if the pins would be high impedance during the off state.

    For the maximum allowable current, on those same pins, you can apply a voltage of 3.3V with an Ammeter in series to the pin to determine maximum allowable current. As the PHY is powered down while you apply this single voltage to that pin, this would mimic the situation that would yield the maximum allowable current.

    Sincerely,

    Gerome