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DP83867E: How to input clock to XI

user4779049
Expert 2155 points
Part Number: DP83867E

Hi Team,

There are several threads on XI input specification topic, however,
I have several questions. Can you advise me on my question related to
the specifications for the XI of the DP83867E

I am designing Ethernet board using DP83867E and has question bellows:

Q1 The datasheet has two parameters for the XI input
      They are VIH/VIL and VOSC.
      I am feeling that they are contradicting each other.
      Referring VIH/VIL, the delta is 0.95V.
      In contrast, VOSC requires 1.4V as the minimum.
      Can you let me know which parameters I should follow?

Q2. VDDIO can be selected among 1.8V, 2,5V and 3.3V.
       XI parameters, VIH/VIL and VOSC can be utilized under these supply conditions?

Q3. When XI is driven from 3.3V LVCMOS, AC coupling is recommended.
      Why the AC coupling is recommended instead of DC coupling with resister divider network?

      I don't thins 500 ohm of resisters does not make clock edge slow. 


Q4. When 3.3V LVCMOs source with two 27 pF capacitor divider is used, the minimum VOSC of 1.4V
        cannot be satisfied.
       3.3V LVCOS Vol <0.4V and VOH>3.3-0.4V, Delta =2.5V divide by 2 = 1.25V
        How do you deal it?

Q5. When Xi is used in AC coupling mode, IX seemed to be biased VDDIO/2.
       If VDDIO=1.8V, the bias level may be 0.9V.
      Under this circumstance, maximum VOSC is applied to Xi, negative peak voltage
       may be 0V.
      If bias level validate some degrees, and 60-40% of duty cycle distortion clock is applied to
      XI, the negative peak may hit the -0.3V which is the absolute maximum ratings.
      Can you use the device under reliable conditions?

Mita

  • 0
    TI__Mastermind 27885 points

    Hello Mita,

    You should follow all parameters specified, VIH, VIL, VOSC for the PHY to work properly. They don't necessarily contradict each other, but instead more specifically define what type of waveform should be connected to that pin. For example, if I follow the spec listed in the datasheet, I can have a waveform that has a VPP of 1.8V with a DC bias at 0.9V which would fit the VIH and VIL spec too. Alternatively, if I had a VPP of 1.6V but had it DC biased at 1.3V (meaning a high of 2.1V and a low of .5), this wouldn't meet the specifics outlined in the datasheet. 

    Please keep in mind that the absolute maximum and minimum voltage levels for the PHY's XI input is [-0.3V,2.1V]. This is static for all VDDIO levels the PHY operates in.

    Figure 28 shows the application for a CMOS oscillator where that VPP is 3.3/2.5V. This would prove troublesome with the absolute maximum/minimum values that are aforementioned. This is why we use a clock divider, using capacitors of equal capacitance to divide the swing by half if the voltage level is 3.3V originally. If it is 2.5V, we can tweak the capacitor divider accordingly like we would a resistor divider.

    Sincerely,
    Gerome