I am using the DP83867IS with a Xilinx FPGA that has the Tri-Ethernet MAC IP core (TEMAC). I interface to the DP83867IS PHY over SGMII 4-wire so I also have in the FPGA a core to bridge the TEMAC's core GMII to SGMII. I am working to configure these cores and make customization as necessary to begin testing the hardware. I would like to be able to run in 10, 100 or 1000.
The SGMII interface is required to always run at 1.25Gbps. As mentioned in the data sheet the PHY takes care of this by elongating the frame replicating each byte 10 times for 100-Mbps. Does it also do this 100 times for 10M if I clear bit[7] of PHY address 0x016F? That wasn't 100% clear in the data sheet.
The issue is the MAC side SGMII core also performs this adaptation replicating bytes so it doesn't seem that both should be doing this. What is best approach? I could disable SGMII auto-negotiation on both the MAC and PHY side and force the MAC/SGMII to run at 1000 all the time (remove that byte replication logic) and let the PHY make replications for 10/100? On the other had it makes more sense for the MAC/SGMII to do this since it has large FIFO's and can throttle as necessary in which case I would need to let the PHY know not to replicate for 10/100. Is that an option?
