Hello, I am working with a design that is concerned with the timing of the JTAG interface on the DP83867E.
We wer able to obtain the below info:
JTAG_TDO: setup 2ns, hold 1.5ns
JTAG_TDI/TMS: setup 5ns, hold 2ns.
We were also able to use the IBIS model to uncover what the high to low propagation delay (tPHL) and the low to high propagation delay (tPLH) for the JTAG signal was but an addition question we have is below:
-What is the clock to TDO skew in regards to the JTAG interface? Also, what is the clock to TDI skew in regards to the JTAG interface?
I could not find the info in the datasheet, is the information available, did I miss it?
