SN65DPHY440SS: Compatibility with Xilinx MIPI IP

Jason Schwartz

Part Number: SN65DPHY440SS

Hi,

We have designed a system that uses the SN65DPHY440SS in the same way as mentioned in sction 8.2.1 of the datasheet. Our source of MIPI data is a Xilinx Artix 7 FPGA and the sink of the MIPI data is a Xilinx Kintex 7 FPGA.

Are there any know issues, limitations, or incompatibilities with using the standard MIPI IP provided by Xilinx?

The retimer part does not every transition into the High Speed state and remains in the Low Power state.

We have a continuous high speed clock going to the retimer which is passing through, but no data on channels 1 or 2 is passing through.

We are satisfying the requirements for the physical interface required by the MIPI standard.

Thanks.

over 5 years ago

0 David (ASIC) Liu over 5 years ago

TI__Guru**** 179406 points

Hi,

Can you try to manually enable the high speed path and see if the data will pass through the DPHY440?

Write Register 0x50 with 8’h1F //Override enable for HS TX path

Write Register 0x51 with 8’h1F //HS TX path enabled.

Write Register 0x61 with 8’h00 // Disable LP path.

Write Register 0x70 with 8’h1F //Override enable for HS RX path

Write Register 0x71 with 8’h1F // HS RX path enabled.

Thanks

David

0 Jason Schwartz over 5 years ago in reply to David (ASIC) Liu

Prodigy 30 points

Hi David,

Thank you for the feedback. We are trying your suggestion now.

Is it possible to get the complete list of registers for the SN65DPHY440SS part?

Thank you.

0 David (ASIC) Liu over 5 years ago in reply to Jason Schwartz

TI__Guru**** 179406 points

Hi,

There are internal design information available with the complete list of register mapping and I can't give out the list.

Thanks

David

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SN65DPHY440SS: Compatibility with Xilinx MIPI IP