DS90UB948-Q1: I2S FIFO underrun/overrun at the same time.

Part Number: DS90UB948-Q1


My SerDes configuration is : DS90UB941 <=> DS90UB948.

DS90UB941 serializes video and audio stream over the FPD-Link III cable. The display panel is having DS90UB948 De-serializer and is attached to the board via FPD-Link III cable. I can see the output video on the display panel but unable to hear the audio. 
I want to transfer audio in data island transport mode. The Host McASP sends audio data with 2 TDM slots.

The Audio codec connected downstream with de-serializer is already configured for 48KHz and 24bit word size. My question is:

  1. I am getting UB948_REG_I2S_CONTROL 0x2B[2]=1 and 0x2B[3] = 1 which means I2S FIFO is underrun and overrun at the same time!! What might be the issue? Please help me find out the issue.



  • Hi Saqib,

    These registers are clear on read. So it is possible they they got trigger at different time. 

    Please read them once and monitor them again to see if there's any over / underrun. 

    Best Regards,

    Charley Cai