DS92LV2411 to DS92LV2412 communication issue

I have also tested in BIST mode, and it still does not function.

Thanks,
John

Hi John,

1). Can you please send us the schematic for the DS92LV2411 as well.

2). Looked at the schematic and noticed RIN+ and RIN- go to test pins(TP17 and TP18). How do these go to the connector.

3). Can you please check or record the strap pins at power up(DS92LV2412)? These set the configuration for the device and we need to make sure this complies with DS92LV2411.

4). DS92LV2412 is sensetive to data polarity. Please make sure CML plus from 2411 goes to CML plus of 2412. ALso CML minus of 2411 goes to CML minus of 2412. 

Regards,,nasser

John,

Would it be possible if we can get your CM DS92LV2412 schematic as well?

Regards,,nasser

1.  I attached the following schematic files: DS92LV2411.pdf; DS92LV2412.pdf

   Please note: On DS92LV2412 that  resistors R23-35, R56,R58 are not populated

2.  Rin+/- are physically routed as a differential pair through Test Points to caps in a straight light.

3. Strap pins are all 0V at power up

4. Confirmed: DS92LV2411 Rout+/- to DS92LV2412 Rin+/- respectively

If say the Straps were all pulled high on a power up could that damage the DS92LV2412?  It was powered up at least once in that configuration.

Also verified that on my DS92LV2412 test board the PDB pin is is pulled high after the VDDIO and VDD inputs per datasheet

I have also attached waveforms for 2411 they are: CLKIN (10.6MHz), Hsync (20KhHz) and Vsync (70hz) ( i know the screen shots say otherwise but that is what my signals are). 

Hi John,

First of all, to answer your question, if straps were pulled high on a power up once this should not damage the device. In any case to make sure the problem you are seeing is not a general issue vs a board stuffing issue please confirm this problem exists on more than one board?

Secondly, if i understand your point correctly, the test point is inline with the trace going to RIN. This means it is not acting like a stub. Please confirm.

1). Please make sure PDB is released AFTER 3.3V and 1.8V supplies are stable. Or you can toggle the PDB pin to activate the strap pins and reset the device. In short, we need to make sure we get a good reset and straps are loaded correctly.

2). Reviewing the schematic and comparing with 2411, nothing stands out. However, we just need to make sure the straps are loaded properly. I noticed the LVCMOS parallel side also goes to the LCD panel(i.e IS LCD STBY). We need to make sure during initial power on reset the LCD panel is not pulling or actively pulling the strap pins. To make sure this is the case, can we disconnect the LS LCD STBY bus just as a test? Or can you please activate/release PDB and then the strap pins(especially Config[1:0] and RFB) should be checked to make sure they are being held low.

3). Please note we read the strap within 1.2mS of when we get out of power up or when PDB goes from low to high. That is when PDB goes high strap pins should be stable for at least 1.2mS so we can reliably latch in the strap pins.

4). You had mentioned DS92LV2412 is idle or not working. Please be more specific and let us know why you think it is not working. Please probe LOCK to see if it gets activated? I am not sure if you can do this since the schematic does not show any trace on this pin.

5). Can you please check the PCB to make sure pins 4 and 58 of DS92LV2412 go to 1.8V? Schematic doesn't show a bubble.

6). Please load R58 even though there is internal pull down on this pin(BISTEN).

Regards,,nasser 

to answer:

There was a board stuffing issue

Test Point is not acting like stub.

1. I have been able to give a good reset

2. Verified voltage levels on straps

3. noted

4. Issue was that the straps were programing the 2412 to be incompatible with the 2411.  Once straps were corrected i was able to get data through the 2412 and to my display in my test set up.

Now i am performing HW tests on my actual HW.  I have the same basic set up as before.   I am having difficulty maintianing a lock on my signal.  The clock will run and the data will lock (LOCK = HIGH) but then it will unlock (LOCK = LOW).  This process will repeat.  but i do not get a steady clock output from the 2412 in my new set up.  I am running the signals from my processor board to my diplay board with twisted pair cable. 

Pixel clock speed = 19.2MHz

Any suggestions?

Thanks,

John

Hi John,

Very glad you were able to debug the original problem.

As to why the device is losing lock, please note if bit error > 0 then we would lose lock. So we have to concentrate on what could be causing bit errors. Can we first try to see if this bit errors are coming from the serializer or the de-serializer? Then below are potential causes of bit error sources: Power supply noise, EMI, signal quality, and gnd noise. Please take a look at potential sources of bit erros.

Regards,nasser

I don't have any meaningful noise on either my power supplies or my GND plane.  I don't have a good way to test EMI at this time, and i have no idea how to evaluate the signal quality of the the Rout/Rin lines. 

how should i test the Rout/Rin lines for signal quality?  What tools and methods should i use?

Thanks.

If I slow down the clock frequency could that improve performance?

Hi John,

You have a good point. Yes by slowing down the clock this may improve the bit error. So please go ahead and slow down the clock rate. I say maybe because this depends on the nature or the root cause of the bit error. If the root cause is related to the high speed CML differential pair then indeed by owering the clock rate we are increasing the bit time and thus this could improve the performance.

To check the high speed signal integrity, we need to use a high speed scope(3GHz or higher) so we can monitor high speed CML eye opening(i.e jitter or peak to peak swing).

Also, you can shorten the cable length between the transmitter and the receiver. This should have the same effect as reducing the clock rate.

I am not sure if you have access to registers but you can program the input equalization.

Finaly, it would be to see if this issue is occuring on the Tx or Rx side. I believe you had mentioned your CM had a board based on DS902412. Can we first make sure your transmitter can drive cable error free into your CM's DS90LV2412 board? If this is fine then we know the problem resides on your receiver board.

Regards,,nasser

Regards,,nasser  

I will check if i have access to a 3GHz scope to try to monitor the eye opening.  I am also going to slow down the clock to 6MHz.

I can set the straps to program the receiver for the input equalization that would be easier than trying to set registers.  Currently it is set to Off.  Should i try to go half way and if it improves continue modifing the equilization from their?

Our processor board (with the 2411) comes tested from our CM with a functional output on their test hardware, which may not be entierly repsentitive of our set up (connections, trace length, etc).  but they say it functions.

This leads me to believe the problem lies either in the interconnections between the boards, signal quality, noise, etc.

Thanks,

Hi John,

It would be great if you can get a scope so we would have a visual indication of what is occurring on the CML side.

Yes please set it to mid point. Then i suppose based on the frequency of the lock going in and out you can either go up or down.

Regards,,nasser

John,

You can try mid point and then by looking at the frequency of the lock going in and out determine whether you need to go down or up.

Based on your CM comment yes i agree it seems it maybe be either the setup or the DS92LV2412 board.

Regards,,nasser

So far i have tried a number of the items discussed with the following results:

1. Soldered Twisted Pair direct to SER vs Intended signal path (through production connectors)

The intended signal path gives a better result (less lock errors) under all test conditions.  I soldered a twisted pair directly to the Rout caps on the SER.  Abaondoning all attempts to test any set up not using the production connectors

2. Slow Down Frequency:

19.2MHz results in almost constant lock error.  Moving to 6MHz reduced lock errors, but does not eliminate them.

3. Reciever Equalization Configuration

7.5dB of attenuation seems to improve the number (reduce frequency) of lock errors at 6MHz clock.  Does not improve 9MHz.  10.5db might be even better.

So now i am curious, what is an acceptable number/frequence of lock errors for video application?  Ideally i would like zero but what should i be able ot live with.

also if i place the devices in BIST mode, what should my patterns look like.  I am still trying to acquire a fast enough scope to check signal quality, but i need a reference to check against.

Thanks

If using the I2C to set the registers are those settings Non-Volatile or do they get reset to the strap settings on a reset or power cycle?

Thanks,

Hi John,

The strap settings are non-volatile. Please make sure you activate PDB after the supplys are stable. This ensures we have a good reset. Also, within 1.2ms after the PDB is released the straps should be stable and are going to be read during this period. Since you are going to use I2C registers, as indicated in the data sheet, the register settings have priority over the strap settings.

Regards,,nasser

So just to be clear if i program the I2C registers once at the time of manufacture, then those settings will override the settings on the strap input pins for every subsequent power up or reset (PBD) without having to rewrite to the registers.

Is that correct?

Or does the I2C only override the strap inputs after power up is complete if sent after every power up?

Thanks

John,

Your 2nd statement is correct. I2C register settings override the strap inputs after the power up is completed.

Regards,,nasser

I am working on getting a >3GHz scope.  i should have it next week some time.  I need some assistance setting up the test for the eye pattern.  can you please send me a schematic as to how i should set it up?  I don't have a scope that can do PRBS but can i just use my data that is going into the serializer?

Thanks,

John

The register settings are reset with a reset or a power cycle, and you must reload them via the I2C interface.

Mark Sauerwald

As Nasser said:

DS92LV2411 Serializer issues were due to noise from processor/switching regulator.  Additional capacitance and ferrite beads resolved the issue. 

DS92LV2412 issues due to improper connection of PDB to supply (battery) voltage of 4.2VDC.  Causing damage to chip.  Once corrected working properly at 5Mhz.

Thanks, John