FPD Link III - DS90UB914 wake up in the wrong mode

Mr Zelinger

The DS90UB913 is particularly sensitive to jitter, and often the pixel clock that comes from the image sensor will have more jitter than the serializer can tolerate - for this reason, we recommend that the DS90UB913Q be provided with an external oscillator from a clean clock source, which is at 2X the rate required by the image sensor, then the 'UB913 will divide this clock by 2, and provide you with a clock that can be used as the reference clock to the image sensor. -  The UB914 should then receive the data and provide you with data and a 12MHz clock at it's output.

I am not certain why your deserializer is powering up in the High frequency mode if you have the MODE pin tied to GND, I will check with my colleagues here to see what might be causing that.

Regards

Mark Sauerwald

One more question - what have you done with the MODE pin on the DS90UB913?  If you are using the PCLK from the imager, then this needs to be tied low as well as the MODE pin on the 914.

The mode pin of the UB913 is connected to GND. We use the clock from the imager.

Dear Mr. Sauerwald,

Thank you for your reply.

The issue is a little bit complicated. We have done some more measurements and compared the signals from the imager and the output signals of the UB914. We found a possibility to overwrite the mode bits so we could check all three modes. The imager delivers 12 bit data, Hsync, Vsync and a clock of 12 MHz to the serializer UB913. Now I describe the results of measuring the output signals of the deserializer UB914 in all modes:

Mode "12 bit low frequency": ROUT0 - ROUT9 = DATA0 - DATA9; HSYNC = DATA10; VSYNC = DATA11; ROUT10 = 0V; ROUT11 = 0V; PCLK = CLOCK / 2

Mode "12 bit high frequency": ROUT0 - ROUT11 = DATA0 - DATA11; HSYNC = ??; VSYNC = ??; PCLK = CLOCK / 1.5

Mode "10 bit high frequency": ROUT0 - ROUT9 = DATA0 - DATA9; HSYNC = HSYNC; VSYNC = VSYNC; PCLK = CLOCK

This behavior is different to the description in the datasheet.

The 10 bit high frequency mode works fine, but we want to transmit 12 bit and our frequency is below the specification of the device. In both 12 bit modes we didn't find the Hsync and Vsync signals at the outputs? We don't want to get a devided clock frequency, we need CLOCK / 1 .

The UB913 could not be used as a clock source in our design because we need these pins as GPIOs.

Hi Matthias,

The results you are observing are not expected. The modes should correspond the following settings:

Can you check the values of register 0x05 on SER and 0x1F on DES in different modes?

Upon power on and initialization, the DES will program the SER (over the bidirectional channel) based on the DES MODE pin setting. It seems like the backchannel data is corrupted during mode setup.

In addition, on 913 datasheet RMODE=0K ohm (PCLK) is incorrect.  Datasheet being updated to RMODE=100Kohm (PCLK).

 RMODE=100Kohm (PCLK), RMODE=4.7Kohm (External Osc)

Dac Tran

SVA APPS

Hi Dac,

we want to use the 12 bit LF mode and the clock source for the SER comes from the image sensor. So I changed the resistors at the mode pins on both pcbs as you described in your table.
DES Rmode = 11k and SER Rmode = 100k

The result is:
- LOCK LED lights on
- SER register 0x05 = 0x14
- DES register 0x1F = 0x04
- the outputs of the DES ROUTx, VSYNC, HSYNC, PCLK are all static high state, no edge, no clock

Best regards,
Matthias

Hi Matthias,

I suspect there’s still a configuration issue. Are you using the SERDESUB-913ROS evaluation board? Can you disconnect the UB913 board and power on only the UB914? Afterwards, read DES register 0x1F and measure the voltage level of the UB914 MODE pin and report back the results.

Dac Tran

SVA APPS

Hi Dac,

the result of the measurement with the DES pcb standalone shows register 0x1F = 04. The voltage at the mode pin is 0.94 V.

We don't use the SERDESUB-913ROS evaluation board. We did our development with the LX16EVK01 EVM snlu013 evaluation kit. Afterwards we designed two pcbs assembled with the DS90UB901 and DS90UB902. These pcbs work fine with our camera. So we decided to use the newer serdes chip set DS90UB913 and DS90UB914 and run into problems. The high speed signal path is designed according the LVDS rules on the pcbs together with Rosenberger HSD connectors and Leoni Dakar cable.

Best regards,
Matthias

Hi Matthias,

The MODE pin reference voltage is incorrect. Can you confirm the voltage divider network on the MODE pins is: 10Kohm to 1.8V with 3Kohm (Rmode) to VSS? To configure 12-bit HF mode, Vout on MODE pin after the voltage divider is: Vout = Vin * (Rmode / (Rmode + 10K)) -> 1.8 * (3 / 3 + 10) = 0.415 V. Your measurement for the mode pin at 0.94 V is corresponding to 10-bit mode.

Dac Tran

SVA APPS

Hi Dac,

sorry for the missunderstanding. We want to use the 12 bit LF mode. As you described in an answer before the Rmode should be 0R to GND. This was our initial situation as mentioned in my first posting: The Rmode was initial 0R and the DES waked up in the wrong 10 bit mode. How could we select the right mode?

Another issue is, we overwrite the mode register to try out all three modes. In the 12 bit LF mode the clock is divided-by-2 internally at the DES output as we measured. In the datasheet is described that this mode devides-by-1 the clock.

Best regards,
Matthias

Hi Matthias,

Thanks for the clarification. Sorry I may have confused the modes. So for 12 bit LF mode, the Rmode configuration is 0Kohm or zero voltage at the MODE pin. Measure the voltage level at the MODE pin to ensure there is no voltage/ground offset. Disconnect the serializer and read the DES register 0x1F=00.

To clarify, the PCLK ratios are related to the linerate of the FPD-Link interface and not the PCLK frequency. With an external PCLK applied the ratio of PCLK is 1:1 from SER PCLK input to DES PCLK output. For example your PCLK is 12MHz; it will be 12MHz on DES PCLK output regardless of the MODE setting and only the FPD-Link linerate is divided. Unless you are running off the internal 25MHz oscillator on SER, then you will see the PCLK frequency divided by the MODE ratio on DES PCLK output.

Dac Tran

SVA APPS

Hi Dac,

I put the mode pin of the DES to GND and read out the register 0x1F, it is 00. Ok, seems to be the target mode 12 bit LF.
The clock from the imager is 12 MHz, sourcing the SER. The clock received at the output PCLK of the DES is still 6 MHz, why ?

What did you mean with runing off the internal 25MHz oscillator on SER?

The register 0x35 of the SER is 00. Is this correct?

Best regards,
Matthias Zeilinger

Hi Matthias,

If DES 0x1f=00, then DES is properly configured in 12-bit LF.

On the SER, can you confirm RMODE=100Kohm (PCLK) for MODE pin? Can you also check if the SER GPIO[0:3] pins (pins 15,16,17,18) are left floating during power up? You should not program Register 0x35 of the SER. On SER, Reg[0x05]=0x10 is for 12-bit LF.

When I refer to ‘internal 25MHz oscillator on SER’, that means if there is no SER PCLK input then device switches over to its on-chip oscillator. If you connect the serdes pair together and power on, then the chipset will lock onto the internal 25MHz oscillator.

Dac Tran

SVA APPS

Hi Dac,

I checked your suggestions. On the SER the RMODE=100K. The pins 15, 16, 17, 18 are floating with a weak pull up Resistor (50k inside the FPGA) to 3,3V. The DES register 0x1f=00 (thats the right 12bit LF mode) but the SER register 0x05=00 !! The output PCLK of the DES is still 6MHz and not the expected 12MHz.

Do you have one more hint for me?

Best regards,
Matthias Zeilinger

Hi all,

are there any new suggestions? We are still working on the implementing of this serial interface. But the output clock is always half the frequency of the input clock ?!

Best regards,
Matthias Zeilinger

Hi Matthias,

The main concern is the setting of the MODE pin on the deserializer. This pin must be properly set upon power on; otherwise device will be configured incorrectly. Also try toggling the deserializer PDB after initial power on to see if the clock frequency changes.

Another alternative to use DS90UB913/914 EVM kit to cross check against your boards; since these boards have been validated.

Dac Tran

SVA APPS