Connecting TFP401 to SN75LVDS83B

Daisuke Maeda

Guru 20205 points

Other Parts Discussed in Thread: TFP401, SN75LVDS83B

The timing requirements seem to be not met to connect the TFP401 and the SN75LVDS83B.

The data setup time of TFP401 is shorter than the data setup time of SN75LVDS83B. The data setup time to ODCK clock edge on TFP401 is 1.8ns (PIXS=low, OCK_INV=low), but the data setup time before CLKIN clock edge on SN75LVDS83B is 2ns.

The data hold time of TFP401 is shorter than the data hold time of SN75LVDS83B. The data hold time from ODCK clock edge on TFP401 is 0.6ns (PIXS=low, OCK_INV=low), but the data hold time after CLKIN clock edge on SN75LVDS83B is 0.8ns.

Can the timing requirements be met?

Best regards,

Daisuke

over 10 years ago

0 Daisuke Maeda over 10 years ago

Guru 20205 points

Hi,

For the timing specifications, all input timing is defined at IOVDD/2 on an input signal in the SN75LVDS83B, but all output timing is defined at VOH or VOL on an output signal in the TFP401.

If IOVDD=3.3, VOH=2.4V and VOL=0.8V, can the timing requirements be met? If PIXS=low and OCK_INV=high, can the rise time from 1.65v (IOVDD/2) on the ODCK clock be more than 0.3ns？

Please give me an answer as soon as possible. Your prompt reply would be appreciated. Please help me if I am confused.

Best regards,

Daisuke

0 Elias Villegas M. over 10 years ago in reply to Daisuke Maeda

TI__Guru* 76130 points

I will review this and provide feedback as soon as possible.

Regards

0 Daisuke Maeda over 10 years ago in reply to Elias Villegas M.

Guru 20205 points

Hi Elias,

Thank you for your reply.

I want to know whether a latched circuit is needed to extend the data hold time after a rising edge of ODCK clock, if PIXS=low and OCK_INV=high.

I hope for your feedback as soon as possible.

Best regards,

Daisuke

0 Daisuke Maeda over 10 years ago in reply to Elias Villegas M.

Guru 20205 points

Hi Elias,

I would appreciate any feedback you can provide regarding the solution to the DVI to LVDS Bridge. If there is better solution, please tell me it.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Elias Villegas M. over 10 years ago in reply to Daisuke Maeda

TI__Guru* 76130 points

Hello,

The set-up and hold times specified for the TFP401 are minimum values operating at the max frequency (165MHz), since the LVDS83B has a maximum frequency of 135MHz there will be no issues on these times since set-up and hold times will be relaxed with lower frequencies.

Regards.

0 Daisuke Maeda over 10 years ago in reply to Elias Villegas M.

Guru 20205 points

Hi Elias,

Thank you for your reply.

Best regards,

Daisuke

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Connecting TFP401 to SN75LVDS83B