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DS90UB913/914 clocking (need help of Dac Tran or Mark Sauerwald88474)

sphinxing
Prodigy 75 points

Hi, Dac and Mark.

Yesterday(12/21/2014) I appended some question to 2 old threads. But I'm afraid that you may miss it since they are too old, so I post a new one. I'm in hurry. So I hope you can give me some answers as soon as possible. Thank you very much.

Related old threads URL as below:
http://e2e.ti.com/support/interface/high_speed_interface/f/138/p/300534/1379578
http://e2e.ti.com/support/interface/high_speed_interface/f/138/t/373603

The following are my question.

Recently, I come across the similar question as Carl's. I'm confused so much. My application is for camera image sensor, i.e. 913 on remote side and 914 on local side of ECU. My image sensor supplies 8-bit parallel data of BT.656 without H/V sync since H/V sync is embedded in parallel data already.

Q1: As P.38 of datasheet says, external OSC(e.g. frequency is 48MHz) feeds GPO3 of 913. After divide-by-2 in 913, GPO2 could supply 24MHz as sensor's clock input. So, sensor's PCLK output should also be 24MHz as PCLK's input of 913. For example, the sensor I'm using does so. Is there any problem with my understanding?

Q2: Then, PCLK of 24MHz will be fed to 913 and divided by 1(12b-LF)/1.5(12b-HF)/2(10b) inside 913. Does this dividing(by 1/1.5/2) block means the same thing as dividing-by-2 block prior to GPO2 output?

Q3: As P.40 of datasheet says, 914 multiplies the recovered serial clock to generate PCLK by 1(12b-LF)/1.5(12b-HF)/2(10b). Up to now, PCLK of 24MHz should be output from PCLK pin of 914. Is this right?

Q4: If the previous is OK, my confusion comes, where can PCLK of 96/72/48 MHz in the table below be found in the circuit? PCLK pin of 913 or 914? Or anywhere else inside 913 or 914? Or the PCLK output from my image sensor? Or, at first, I should decide external OSC of 913 by image sensor OSC? In fact, my image sensor outputs 8-bit parallel data with 27MHz clock and requires 27MHz OSC. Since ratio in the table below should be 2, so I have to feed 13.5MHz external OSC to GPO3 of 913, and then GPO2 will output 6.75MHz for sensor unit. And prior to input to sensor clock, I have to multiply 6.75MHz by 4 to get 27MHz required. How can I deal with this trouble?

Mode

GPIO3 XCLKIN

GPIO2  XCLKOUT = XCLKIN / 2

Ratio

PCLK frequency = XCLKIN * Ratio

10 bit

48 MHz

24MHz

2

96 MHz

12 bit HF

48 MHz

24MHz

1.5

72 MHz

12 bit LF

48 MHz

24MHz

1

48 MHz

Q5: BTW, I need to use GPI function for motion detection(status bit reported by image sensor) on 913 side. Since 913 has no GPI function pin, can I use H/V Sync pin or other video data pins like DIN[1] or DIN[0] as GPI instead since I only use 8-bit video data? And on the 914 side, I connect the corresponding pin to ECU for use. Does this idea work? If not, why not? If yes, is there any disadvantage or side effect? In my opinion, motion detection signal will be sampled on PCLK rising edge. Maybe this results in some precision error. But is this error serious enough to be not able to work correctly at all? And will reliability of video data get involved with this pseudo GPI?

Thanks Dac and Mark for your help.
By sphinxing.

  • 0
    TI__Expert 7395 points

    Hi sphinxing,

    In order to use the 913/914 external oscillator mode, the specified ratios (1/1.5/2) must be for 1(12b-LF), 1.5(12b-HF), and 2(10b). The ext oscillator mode is intended for camera sensors with excessive PCLK jitter beyond >0.1T (10% jitter PCLK period). If your sensors have relatively low jitter and good performance, then I suggest using the direct PCLK mode on 913.

    A1: In ext osc mode, GPO2/CLKOUT should be connected to the sensor’s XCLK input (oscillator/crystal). In 10b ext osc mode, if the osc is 48MHz on GPO3 input, output is 24MHz on GPO2, and PCLK input (913 pin 3) must be 96MHz.

    A2: On 913, the PCLK will be internally divided by the corresponding 1(12b-LF), 1.5(12b-HF), and 2(10b). The mode dividing block is different than GPO2 block because, GPO2 -> GPO3 is always half.

    A3: If both 913/914 modes match, then the PCLK will remain the same frequencies.

    A4: You need to follow the table and mode ratios.

    A5: Yes, you may transmit any data signal on DIN[x] or HS/VS pins. The only restriction is HS/VS are limited to no more than one transition per 10 PCLK cycles under 10bit mode; 12b-LF/HF have no restrictions.

    Dac Tran

    SVA APPS

  • 0 in reply to Dac Tran
    Prodigy 75 points

    Thank Dac for your helpful reply.

    In general, for most sensors, input REF CLK is always 4x multiplied to generate output CLK internally(i.e. 24 -> 96MHz). Unluckily, I'm using a sensor with ref input and output CLK both of FIXED 27MHz. So, it's likely that I use either clock multiplier device as REF CLK input of sensor or direct PCLK mode instead of EXT OSC mode.

    Your explanation of HS/VS is very important and useful. I hope that it would better be mentioned in datasheet.

    Sphinxing.