DS125DF1610 locking.

Hi Yuval,

1. Technically, yes, you can use the pattern generator without a data input to the chip by putting the device in free run mode. However, the data rate will not be as precise as when the DF1610 locks onto a known data input that operates at a fixed rate. This could be problematic if you need to output a specific data rate, such as a 10.3125 Gbps signal, and the DF1610 transmitter's free run mode does not give you the appropriate amount of precision to be used in your system.

2. Yes, you can generate patterns at different rates for each channel. Each channel has its own VCO group and CAP DAC settings that can be applied independently.

3. Yes, if the CDR is locked to an input signal, the pattern generator's frequency will be locked with that of the incoming data. If you wish to lock to higher frequency multiples of the input signal's data rate (not exceeding the VCO frequency), then you can accomplish this by disabling single bit transition checking.

I would recommend that, in order to run the pattern generator at a certain desired rate, you should apply a clock signal at the input that is a divide-by-2 or more factor of the VCO operating range. This means applying a divide-by-2, 4, 8, or 16 clock on the input. (Remember that to convert the clock frequency in GHz looks like a "1010" data pattern that is operating at double the frequency in Gbps.) From there, you will be able to output a fixed pattern from the DF1610 output that is operating at a known data rate rather than at a less consistent free-run setting.

Thanks,

Michael

Hi Yuval,

Thanks for your patience this past week. We were on holiday in the U.S. this past week.

I do not expect you to lock onto a 312.5 MHz reference clock. The reason for this is because you will only be able to lock onto divide-by-2, 4, 8, or 16 value with relation to the VCO operating range. Since the operating VCO range for the DS125DF1610 is 9-12.5 GHz, the minimum clock that you will be able to lock to is 9 GHz / 16 = 562.5 MHz.

With that having been said, it may still be possible to lock onto a 312.5 MHz clock signal at the input if you disable Single-Bit Transition checks (in order to enable locking at sub-harmonic rates of the actual operating rate), since 312.5 MHz is a divide-by-32 factor of 10 GHz.

Thanks,

Michael

Hi Yuval,

The internal VCO must operate at least twice as fast as the fastest frequency presented by the data. If we looked at a '1010' pattern at 9-12.5 Gbps, it would be the same as looking at a 4.5-6.25 GHz oscillator. Therefore, in order to sample 9-12.5 Gbps data accurately, the VCO must be running at 9-12.5 GHz. Thus, in the datasheet we state that we can lock to 9-12.5 Gbps data, but internally, the VCO is running at 9-12.5 GHz, and the divide-by ratios allow the retimer to lock to subrates of the VCO lock range.

I believe you will have better success locking to an input clock at 625 MHz.

Thanks,

Michael

Hi Yuval,

In the situation that you are using the DS125DF1610, you should not have a decreased performance as a result of disabling SBT, since you are using the 625 MHz clock input to the DF1610 as a reference clock type input.

Your question got me thinking about how the device would behave if we disabled SBT checking in general. After discussing with my colleagues, I have realized the following. From the perspective of using the DS125DF1610 in "mission mode," meaning the regular operating mode where the device is used between two endpoints to recover incoming data and retime the output, disabling SBT checks may ultimately result in you incurring a smaller input jitter tolerance budget due to the decreased UI, since the clock will be attempting to capture data at a higher data rate than is actually presented at the input of the DF1610. While this may not necessarily result in more bit errors, capturing at a higher data rate than necessary may be more problematic in a particularly noisy or lossy scenario. Thus, in mission mode, we recommend keeping SBT enabled.

Thanks,

Michael