This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB947-Q1: Could you kindly help to help to check the DS90UB947's issues?

Part Number: DS90UB947-Q1

Dears:

Could you kindly help to help to check the DS90UB947's issues:

1. Can we reset several times of PDB pin after DS90UB947's power on?

2. Is there any time series diagram between DBP and  1.1V, 1.8V, clk after DS90UB947's power on?

3. Whether do FPDLLINK connect between DS90UB947 and DS90UB948 under the default parameter?

Pls. kindly help to us!

Luck Wu

  • Hello,
    is there any reason for reseting PDB several times?

    The recommended power up sequence is as follows:
    VDD18, VDD11, wait until all supplies have settled, activate PDB, then apply OpenLDI input.

    using the default register values, you would have Link and LOCK if you have a video source active and both devices, SER and DES, are configured via Hardware (Mode Pins)
  • Hi Hamzeh:

    Since we are handling the issues about DS90UB947 and 948, you can refer the below website:

     Can we reset PDB several times? If we can how could we do?

    And another issue is when does 947 send data to 948 after 947 receives clock signal or DE signal?

    Is there any requirement about 947 sending data to 948?

    Pls. kindly help us!

    Thanks a lot!

    Best regards

    Luck Wu

  • Hello,
    What is the purpose of issuing PDB several times? When you toggle PDB (high -> low -> high) the low pulse should meet a minimum duration of 2ms. The PDB should only be activated after all power supplies have reached steady state. Also the input pixel clock for 947 needs to be stable without frequency drifts before PDB is applied.

    In your system, is the 947 up and running first and sending data to 948 before the deserializer side is powered up? This will help guarantee deterministic startup behavior in your system.