Multiple RS422 signals are to be terminated in FPGA.
Using the SN65HVD09 transceiver, Side A gives the TTL output which are to be terminated on FPGA IO pins & this is a 5V part.
The Question is whether we need to use a level shifter on side A for all TTL out??? to connect to FPGAs? .
FPGA IOs are at 3.3 max
-Sathiyanathan
