TUSB9261-Q1: Questions about the specification

Hello,
1.
(Q1) Your design needs to meet the requirements described in "7.3.1.4 Power-Up and Reset Sequence" section.

(Q2) We recommended duration of the GRSTz input is greater than 2 ms but less than 100 ms.

(Q3) There is no concern about the power down sequence.

2.
(Q1) If you are using a crystal you need to connect it as described on figure 3 of the Data sheet.

(Q2 ) You should not connect VSSOSC to GND if you are using a crystal.

3.
(Q1) After the boot code loads the firmware the device configure the SATA advanced host controller interface host bus adapter (AHCI)
and the USB device controller. please note the OS need to load the Mass Storage device driver to.

4.
(Q1) Could you please detail what do you want to modify?

Regards,
Roberto

Hello Roberto,

Thank you for your reply.

>(Q1) Your design needs to meet the requirements described in "7.3.1.4 Power-Up and Reset Sequence" section.

Regarding this answer,
On "TUSB9261-Q1" (Automotive) datasheet (link below)
There is no section of "7.3.1.4 Power-Up and Reset Sequence".

www.ti.com/.../tusb9261-q1.pdf

Are you referring to the "TUSB9261" (non Automotive) datasheet?
Regarding "TUSB9261 - Q1" (Automotive), is it correct to refer to the "TUSB9261" (non - Automotive) data sheet?

Best Regards,Orobianco

Hello,

Even when the Q1 datasheet not mentions it we recommend following the Power-up sequence mentioned in the No-Automotive version.

Regards,
Roberto

Hello Roberto,

Thank you for your reply.
I'm sorry to trouble you, but please let me ask additional questions below.

<Q1>
Regarding reset at power-on,
Which timing should be used as the starting point to deassert the reset(GRSTz) greater than 2 ms but less than 100 ms?
Since the following information is described in "7.3.1.4 Power-Up and Reset Sequence" section (Page 12) of the TUB9261 data sheet,

>A minimum reset duration of 2 ms is required.
　　>This is defined as the time when the power supplies are in the recommended operating range to the deassertion of GRSTz.

Is it correct in understanding that resetting is released within 2 ms or more and 100 ms from the timing
when all the power supplies of VDD (Core 1.1 V), VDD 33 (IO 3.3 V), and VDDA 33 (Analog) reach the recommended voltage range?

<Q2>
What kind of problems will occur if reset is not released even after 100 ms or more?

<Q3>
What kind of problems will occur if VDD33 and VDDA33 rise before VDD in the power-up sequence?
My customer's PCB is already completed so that VDD33 and VDDA33 rise before VDD, is it necessary to change?

<Q4>
When using crystal, what kind of problems will occur if VSSOSC is connected to GND?
My customer's PCB is already completed with VSSOSC and GND connected, is it necessary to change the PCB pattern?

<Q5>
Do I need to load the mass storage device driver every time the device boots?

<Q6>
How long will it take for a maximum from reset cancellation to loading mass storage device driver?

<Q7>
Regarding booting firmware,
How long will it take for a maximum from reset cancellation to ready to access device?

<Q8>
About mass storage,
In addition to the loading of the mass storage device driver, is there any need to control the device intentionally from the host side?

<Q9>
>Could you please detail what do you want to modify?
=>There is no particular place I would like to modify at the moment, but could you please tell me as information?

<Q10>
When writing firmware directly to SPI Flash memory with FLASH programmer instead of Flash Burner,
is there any problem by writing FF to the unused area other than the area where firmware is written?

Best Regards,Orobianco

Hello Roberto,

Thank you for your reply.
I'm sorry to trouble you, but please let me ask additional questions below.

<Q1>
Regarding reset at power-on,
Which timing should be used as the starting point to deassert the reset(GRSTz) greater than 2 ms but less than 100 ms?
Since the following information is described in "7.3.1.4 Power-Up and Reset Sequence" section (Page 12) of the TUB9261 data sheet,

>A minimum reset duration of 2 ms is required.
　　>This is defined as the time when the power supplies are in the recommended operating range to the deassertion of GRSTz.

Is it correct in understanding that resetting is released within 2 ms or more and 100 ms from the timing
when all the power supplies of VDD (Core 1.1 V), VDD 33 (IO 3.3 V), and VDDA 33 (Analog) reach the recommended voltage range?

<Q2>
What kind of problems will occur if reset is not released even after 100 ms or more?

<Q3>
What kind of problems will occur if VDD33 and VDDA33 rise before VDD in the power-up sequence?
My customer's PCB is already completed so that VDD33 and VDDA33 rise before VDD, is it necessary to change?

<Q4>
When using crystal, what kind of problems will occur if VSSOSC is connected to GND?
My customer's PCB is already completed with VSSOSC and GND connected, is it necessary to change the PCB pattern?

<Q5>
Do I need to load the mass storage device driver every time the device boots?

<Q6>
How long will it take for a maximum from reset cancellation to loading mass storage device driver?

<Q7>
Regarding booting firmware,
How long will it take for a maximum from reset cancellation to ready to access device?

<Q8>
About mass storage,
In addition to the loading of the mass storage device driver, is there any need to control the device intentionally from the host side?

<Q9>
>Could you please detail what do you want to modify?
=>There is no particular place I would like to modify at the moment, but could you please tell me as information?

<Q10>
When writing firmware directly to SPI Flash memory with FLASH programmer instead of Flash Burner,
is there any problem by writing FF to the unused area other than the area where firmware is written?

Best Regards,Orobianco

Hello,

Q1. yes, that is correct.

Q2. Since that is possible that some power rails be out of recommended range we can ensure the correct device behavior.

Q3. The internal block requires this order of the power rails for the correct function of the device. If the power-up sequence detailed in the datasheet is not followed the device will not work properly.

Q4. You should not connect VSSOSC to GND if you are using a crystal as described in the DS.

Q5. The mass storage driver will be loaded until the TUSB9261 is connected to the Operating System.

Q6. As the mass storage driver is loaded by the Operating System it depends on your system speed.

Q7. This time is not defined because this depends on several factors SPI speed, firmware size, even the length of the traces.

Q8. You'll not require any additional requirement.

Q10. Yes add FF to unused space data, please note that additionally to the firmware you require to write the headers to the EEPROM, you can use the TUSB926x Flash burning tool to generate a full EPROM image (headrs+firmware), just need to follow section "4.8 Exporting the Firmware Data to a File" and you can use this generated file on any Flash programmer.

Regards,
Roberto

Hello Roberto,

Thank you for your reply.
I'm sorry to trouble you, but please let me ask questions below.
---------------------
(1) I can not understand well about your answer below, so please let me ask you a question again.

>Since that is possible that some power rails be out of recommended range we can ensure the correct device behavior.

Does your answer mean that the power supply voltage may be out of the recommended range if you hold the reset to low over 100ms?
If so, why does the power supply voltage fall outside the recommended range with a reset of 100 ms or more?
In the case of a reset of 100 ms or more, the start of system operation may be delayed, but I do not know the reason why the problem occurs other than that.
Could you tell me the principle that causes problems in operation?


(2)Please let me confirm the following answer.

>This time is not defined because this depends on several factors SPI speed, firmware size, even the length of the traces.

If the host microcomputer does not know when to start accessing to TUSB9261-Q1, the host microcomputer can not start communication to TUSB9261-Q1.
Is there a READY signal for TUSB9261-Q1 communication?
How do I know the communication READY timing of TUSB9261-Q1?
---------------------

Best Regrds,Orobianco

Hello Roberto,

My customer is waiting for your answer, so I expect prompt answers.
I'm sorry for the trouble.

Best Regards,Orobianco

Hello,

Sorry for the delay.

1 I'm working on this we are taking a look at the background of the reset time, Are they planing to have a reset time longher than 100ms?

2 Then can monitore the PWM1, it will start a heard beat when the firmware is loaded and working.

Regards,
Roberto

Hello Roberto,

Thank you for your reply.
I will comment below.

>I'm working on this we are taking a look at the background of the reset time,
>Are they planning to have a reset time longer than 100ms?

==> I will check with customers whether the customer reset time is 100ms or not.
And I will feed back the result to you.
==> 2017/12/18
I confirmed with the customer.
Customers need to continue resetting for more than 100 ms due to their constraints on their system.

>Then can monitor the PWM1, it will start a heard beat when the firmware is loaded and working.

==> How can I check that TUSB9261-Q1 communication preparation is complete from heartbeat?
About heartbeat There is no detailed description in the data sheet,
so I do not understand how to use it. Could you give me detailed documentation?

Best Regards,Orobianco

Hello Roberto,

> I will check with customers whether the customer reset time is 100ms or not.
>And I will feed back the result to you.

==> 2017/12/18 Update
I confirmed with the customer.
Customers need to continue resetting for more than 100 ms due to their constraints on their system.
Does the problem occur if the reset is continued for 100 ms or more?
If there is a problem, please tell me the reason why the problem occurs.

>Then can monitor the PWM1, it will start a heard beat when the firmware is loaded and working.

==> How can I check that TUSB9261-Q1 communication preparation is complete from heartbeat?
About heartbeat There is no detailed description in the data sheet,
so I do not understand how to use it. Could you give me detailed documentation?

Could you please answer the above?

Best Regards,Orobianco

Hello,

I confirmed with designers and the reset pulse can be longer than 100ms just hey need to make sure it is at least 2 ms.

Regarding how to know when the device is ready I think is better if you monitor GPIO7 it will indicate when the SS connection is detected. because the PWM1 will start when the firmware be ready but it doesn't mean you have a USB connection.

Regards,
Roberto

Hello Roberto,

Thank you for your reply.
I will comment below. Please confirm and reply.

>Regarding how to know when the device is ready I think is better
>if you monitor GPIO7 it will indicate when the SS connection is detected.
>because the PWM1 will start when the firmware be ready but it doesn't mean you have a USB connection.

As a result of confirming with my customer, he would like to know the timing of completion of firmware loading
So I think that PWM 1 should be monitored.

I do not understand the specification of PWM 1 in detail.
The data sheet is described as "SW heartbeat",
but in the application note "Power indicator LED." Is stated.

(Q1) Which specification is correct?

In the case of Power indicator LED. I think that I can not do what I intended.

Although this terminal is specified as PWM, on the application note, it seems to be Duty 0%: High / Low pin.
Since there is no description in the data sheet, would you please tell me about the following contents?

(Q2) What is the condition to become High / Low?

(Q3) In order to control the duty, what should I set for the device? （ex.register)
Does PWM 1 operate with a duty other than 0%?

(Q4) Although PWM 1 is described as heartbeat, is it OK to understand that FW is loaded and communication is possible with both SATA and USB?

(Q5) If there is a recommended startup sequence until confirming the firmware loading completion, please tell me about it.

Best Regards,Orobianco

Hello Roberto,

Thank you for your reply.
I will comment below. Please confirm and reply.

>Regarding how to know when the device is ready I think is better
>if you monitor GPIO7 it will indicate when the SS connection is detected.
>because the PWM1 will start when the firmware be ready but it doesn't mean you have a USB connection.

As a result of confirming with my customer, he would like to know the timing of completion of firmware loading
So I think that PWM 1 should be monitored.

I do not understand the specification of PWM 1 in detail.
The data sheet is described as "SW heartbeat",
but in the application note "Power indicator LED." Is stated.

(Q1) Which specification is correct?

In the case of Power indicator LED. I think that I can not do what I intended.

Although this terminal is specified as PWM, on the application note, it seems to be Duty 0%: High / Low pin.
Since there is no description in the data sheet, would you please tell me about the following contents?

(Q2) What is the condition to become High / Low?

(Q3) In order to control the duty, what should I set for the device? （ex.register)
Does PWM 1 operate with a duty other than 0%?

(Q4) Although PWM 1 is described as heartbeat, is it OK to understand that FW is loaded and communication is possible with both SATA and USB?

(Q5) If there is a recommended startup sequence until confirming the firmware loading completion, please tell me about it.

Best Regards,Orobianco

Hello Roberto,

I am sorry for the delay in response from me.
As for SW heartbeat, my customer is confirming their operation on their board, so if they have any questions, we will contact you separately.

I received a new question from my customer.
Would you please give me an answer ?

<Question>
The customer wants to evaluate the signal waveform output from the TUSB9261 to the SATA device.
For easier evaluation, is there a function to output a test signal from the TUSB9261 to the SATA device?
(Previously, when a customer used another company's SATA bridge IC, the IC seems to have four kinds of test patterns.)
(They seem to expect similar features to TUSB 9261.)
If TUSB9261 does not have the same function, is HOST USB sending a command to TUSB9261 to output SATA signal is a realization method?

Best Regards,Orobianco

Hello Roberto,

I think that there was contact with you from TI Japan. My customer do not have NDA with Synopsys.
Are there any other alternative ideas?
Is it the only way to send a command from HOST to TUSB9261 - Q1 and output SATA signal?

Apart from this, I received additional following questions from my customer.
Sorry to trouble you, but Would you please give me a reply ?
---------------------
Q1.My customer has a question about your following previous answers.

>Dec 2, 2017 5:26 AM
>Q3. The internal block requires this order of the power rails for the correct function of the device.
>If the power-up sequence detailed in the datasheet is not followed the device will not work properly.

Regarding the power-up sequence, if the VDD rise within the recommended operating range
before VDD33 and VDDA33 rise to the recommended operating range, will the device operate correctly?

Q2.Is there a specification for the ripple voltage of the power supply?
　 Regarding the 1.1 V(VDD) power supply line, I found the following answer at E2E.

e2e.ti.com/.../2177957 RIPPLE#2177957
=> 1.1V is most sensitive. you will need to limit the ripple +/-20mV.

Would you please tell me the ripple voltage specification of VDD33 (3.3 V) and VDDA33 (3.3 V)?

Q3. Is there a time specification of the rise and fall of the power supply voltage?
(For example, is there a specification that it is necessary to rise up or fall down in X (ms) time from X (V) to X (V) voltage?)

Q4.Is there a voltage specification that the voltage must drop below X (V) when turning off the power supply?

Q5.Is there a time specification (Tr / Tf) for the rising and falling of the reset terminal (GRSTz)?

Q6.Is there a possibility of ignition or smoking if shorting (10 k ohm) the adjacent terminals of the IC due to condensation?

Q7.When dew condensation causes the adjacent terminals of the IC to short (10K ohm), will return to normal operation when the normal power up sequence is executed after condensation stops?

Q8.Is there a recommended oscillation margin for crystal?
---------------------

Best regards,Orobianco

Handled through e-mail.

Regards,
Roberto

Hello Roberto,

I sent the answer obtained via TI Japan to my customer.
As a result, we received the following additional questions from customer.
Sorry to trouble you, but Would you please give me a reply ?

Q1. In the previous question, I got an answer that crystal oscillation frequency deviation is +/- 50 ppm.
　　Is this the specified value in the operation guaranteed temperature range (-40 to 85 ° C) of TUSB9261-Q1?

Q2. When resetting TUSB9261 - Q1 while running TUSB9261 - Q1,
　 Is it reset correctly even with reset time of minimum 2 ms?
　　Also, in that case, is there any other necessary sequence?

Thank you for your help.
Best Regards, Orobianco

Hello Roberto,

I received an additional question from the customer. Would you please answer the following questions?

Q1. About crystal oscillation tolerance ± 50 ppm, Frequency stability (1 year aging) ± 50 ppm is written in the data sheet.
Does this means that for frequency tolerance of ± 50 ppm, a further deviation of ± 50 ppm is permitted after 1 year,
allowing a deviation of ± 100 ppm in total? Or does it mean that the deviation must be within ± 50 ppm even if it is used for one year?
（In both cases, operating temperature condition: at -40 to 85 ° C）

Q2.When using crystal, is there a specification of amplitude level (amplitude voltage) as input specification of XI pin?
Concretely, with respect to Vp-p, Vinl threshold, Vinh threshold,If there is regulation of voltage value, please let me know these value.

Thank you for your help.

Best Regards,Orobianco