I have a questions regarding the layout. Is it possible to place 2 of these ISO7761 back to back (top and bottom) on a 93mils thick PCB?
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Thank you for posting, and welcome to E2E! An example of this idea is shown below:
Yes, it is okay to place two ISO7761 or other isolation devices on the top and bottom of PCBs so long as the isolation barrier and creepage/clearance distances are fully preserved on both sides of the board and throughout the internal layers as shown above.
Please let us know if you have any additional questions.
Thanks very much Manuel! This helps.
A follow up question, if my application doesn't need galvanic isolation but I only use it for EMI purposes. Do I still need to implement the isolation in PCB? in other words, do I need to implement the PCB voids under the part? if yes, what happens if I have copper shapes/traces etc. right under the part (on layer 1) and other layers?
Thanks for elaborating on your question.
The separation and spacing between the two sides of device are purely for isolation purposes. This spacing need not necessarily be of the width of device, it can be anything that the application requires. If the application has no isolation requirement then no spacing is needed.
The separation here refers to a space void of traces, planes and shapes. If separation isn't needed then these traces, planes and shapes can be run under device without any issues.
Could you please elaborate on what EMI requirement you are trying to achieve using isolators? Please note that if this EMI test is high voltage transient test like IEC 61000-4-2 ESD, then separation across the isolation barrier is needed to support the clearance required by the high voltage transient to avoid air breakage. Hence, please let us know your EMI requirement and I can comment if the spacing on PCB is needed or not and how much. Thanks.
hi Koteshwar, since the isolator isolates the two 'sides' (analog or digital, high freq or low frequency etc), isn't it correct that it also reduce or eliminate the common mode noise hence potential EMI? So my question was mainly, if I use it for this purpose alone, do we still need to implement the layout guidelines.
EMI is a very broad term, it needs to defined to individual noise sources to understand how they can affect system and use methods to minimize their impact. Isolator can help address some of them, which include ESD, EFT and Surge among others.
Like I mentioned earlier, if you do not maintain sufficient spacing according to the noise transient requirement then the air can break and couple noise parasitically through small spacing. For example, to support 8kV IEC ESD across the isolation barrier, the minimum spacing (clearance) to be maintained is 6mm. Any smaller spacing may lead to air breakdown and noise coupling parasitically, leading to signal integrity or other failures.
Hence, please do ask customer to know EMI issues do they need to meet and share with us so that we can comment if isolator is needed for that or not and if it is enough to protect against all of them.
I will go ahead close this thread, once you have inputs from customer, you can create a new or related question as a separate post. Thanks.