• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 13 subscribers
  • Views 522 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISOW7842: Is it correct behavior that ISOW7842 Vcc terminal input current waveform becomes a triangle?

Kazuya Nakai59
Guru 21675 points
Part Number: ISOW7842
Other Parts Discussed in Thread: ISOW7742

Hello guys,

One of my customers is evaluating ISOW7842 for their new products. 
They monitored VCC terminal input current waveform with the following conditions.

1. 10uF and 0.1uF ceramic capacitors are attached between VCC and GND1, VISO and GND2 with the minimum distance (less than 2mm).

2. VCC voltage is 3.3V, VISO is 5V.

3. Input signals of VCC side (INA, INB) is L level fixed.

4. Input signals of VISO side (INC, IND) is L level fixed.

5. Output signals of VISO side (OUTA, OUTB) are connected to a CMOS logic gate IC input terminal each.

6.VCC terminal of the CMOS logic gate IC is connected to VISO terminal.

They observed at VCC that triangle current waveform (peak=400mA, bottom level=almost 0mA, waveform bottom width=5us~8us, period of peak current to next peak current timing= about 50us).

Is this correct behavior of ISOW7842?

I think this is the current flowing in the transformer winding on the VCC side at switching to generate VISO voltage.
Also I think the period is long (a behavior like pulse skip mode) because VISO terminal load is light.
Is my understand correct?

Your reply would be much appreciated.

Best regards,
Kazuya.

      

  • 0
    TI__Guru 55815 points

    Hi Kazuya-san,

    Thanks for reaching out and for sharing detailed inputs related to your question.

    Yes, triangular current waveform at the input is expected. The waveform width and period values that you have specified for light load conditions are also the expected values.

    Kazuya Nakai59 said:
    Also I think the period is long (a behavior like pulse skip mode) because VISO terminal load is light.
    Is my understand correct?

    Your understanding is mostly correct. The device doesn't have defined operating modes but it does vary switching frequency based on load to achieve the best efficiency all the time. For lower lights, the switching frequency is going to be lower and for higher loads the frequency is higher. Hence, you seeing a lower switching frequency for light loads is according to device expected operation.

    If this is a new customer design, we recommend you to use our second-generation isolator with integrated DC/DC ISOW7742 that offers significantly better performance and the lower emissions over ISOW7842.

    Let me know if you have any other questions, thanks.


    Regards,
    Koteshwar Rao