Tool/software:
Dear team,
We are using the part number ISOW7841FDWER for digital isolator in BMS.
On primary side the 3.3v is connected through Power management IC(low voltage(LV)-12v I/P) and on secondary side the BMIC(battery monitoring IC ) is connected(high voltage(HV)-60v I/P).
the isolation barrier is their for the primary and secondary sections for digital isolator IC and communicated through SPI interface i.e the BMIC is on secondary side connected through SPI to LV.
case1:-
When LV IS ON/ OFF the CS on secondary is pulled high and VREG FOR BMIC IC is not getting OFF.
When digital isolator is removed from board, the CS on secondary is pulled high and VREG FOR BMIC IC is getting OFF.
So the intended functionality is when LV goes off the digital isolator should go off and does have any enabled condition for CS and BMIC IC vreg should go off.
Will digital isolator cause any powering to the secondary load because of capacitive coupling and cause vreg to observe 5v as( CS pin is even pulled high)?
Best regards,
Navya.d
