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ISO7762-Q1: SPI delays: pulse width distortion and channel-to-channel skew

Other Parts Discussed in Thread: ISO7762

Tool/software:

We are using isolator ISO7762 in a 5 wire SPI bus and need to ensure we can achieve the max data rate 6 Mbps up to 125C. There a number of devices in the path but this IC adds the highest propagation delay, In estimating the worst-case delays, should we include the pulse width distortion and the channel-to-channel skew. in addition to the pulse width distortion and the channel-to-channel skew values, especially between Clk and MOSI? 

  • Correction: 4 wire SPI

  • The pulse width distortion describes differences between rising and falling edges.
    The channel-to-channel skew described differences between channels.

    You can ignore the pulse width distortion for your calculations. However, please note that the clock and MOSI are transmitted from side A to B, the device reacts to the clock, and MISO is then transmitted from side B to A. So the skew between CLK and MOSI (as seen by the slave) is completely specified by the channel-to-channel skew, but the skew between CLK and the returned MISO is two times the propagation delay.