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ISO6741: Long-distance SPI communication

Rafael Savariego
Prodigy 60 points
Part Number: ISO6741

Tool/software:

Hello!

I have been thinking about a modular design consisting of 3 main parts (see picture below):

  • Main board: Consisting of the main MCU, the copper tracks to connect one of the SPI controllers to communicate with M=10 daughter boards via M=10 edge connectors and a board-to-board connector to connect a future extension board.
  • Extension board: Formed by the board-to-board connector complementary to the main board, the copper tracks to connect the daughter boards to the SPI bus and the edge connector to connect the different daughter boards.
  • Daughter boards: Small boards with specific functions. The integrated circuits on this daughter board communicate with the main uC through an isolated SPI bus (each daughter board will include an ISO6741).

Block diagram

The idea is to communicate the main MCU with all daughter boards using an SPI interface with a 10 MHz clock signal, but I am concerned about a few points:

  1. The distance between the main MCU (uC) and the last daughter board on the main board (E_A_M). This distance will be about 30 cm. Is this distance of concern in the context of SPI communication at 10 Mhz clock signal?
  2. The termination circuit for that SPI communication. Based on some forum reading, I think I need to add a termination circuit to that SPI communication (after the last daughter board of the main board). The problem is when I want to add the extension board, after the termination circuit. Should I add a SPI repeater on the extension board (after the termination circuit) or do I need to add another termination circuit on that board?
  3. The extension board will be about the same size as the main board, so the first question applies here as well, only the distance between the main MCU and the last daughter board of the extension board (E_B_N) will be about 60 cm.
  4. I have read the tidued8 document and I am not sure if I need to use a SPI+LVDS approach instead of a single-ended SPI bus.

Thank you very much for your help.

  • 0
    Guru 317250 points

    1. What is the total capacitance? All those traces and connectors add up. But I'd estimate that 10 MHz should be possible.

    2. Typically, SPI goes into high-impedance inputs, and you'd use source termination. Adding buffers is possible, but those will increase the propagation delay.

    3. What is the total capacitance?

    4. While differential transmission would allow longer distance, it is mainly used to reduce noise sensitivity. What environment do you expect? (Why are the daughter boards isolated?)

  • 0 in reply to Clemens Ladisch
    Prodigy 60 points
    1. Currently I do not have a rough idea of the total capacitance, I will get it during the PCB design process. The input capacitance of the ISO6741 is about 2.8pF, so, making a rough approximation 2.8 * 10 = 28pF + the capacitance added  by the the printed circuit board tracks.... Let's say 100 pF (I'm not sure).
    2. Could you please provide me with information on the use and design of the termination at source? Yes, I understand that adding buffers on the expansion board will increase the propagation delay, but I'm not sure how to do that considering that the main board will have a board to board connector for future expansions (the expansion board in the picture).
    3. The double of 1 (~200 pF).
    4. The environment I expect is industrial. The daughter board will be isolated because it will be testing devices that are likely to be faulty and powered by 24 / 48 V rails. The main reason to isolate that board from the main board is to minimize damage if something bad happens on the "high voltage" side of the daughter board.

    Thank you very much for your reply.

  • 0
    TI__Mastermind 29375 points

    Hello Rafael, 

    Thank you for the detailed description of the problem. As stated in the app note, SPI communication was designed for short, on-board communications. From your description, moving to an LVDS set-up would be a good approach. LVDS is intended for short distance off-board communication, and the differential signaling would allow for the design to have higher noise immunity and communicate at faster data rates. 

    1. The 30cm distance is possible, since this distance seems short enough. Please make sure to account for the transmission delay as well. 
    2. From my understanding, this would depend on the type of termination used. Logic outputs typically cannot drive a lot of current, and therefore the typical resistor to GND termination would not be possible (usually 50 or 100-ohm). It would be preferable always have termination on the two farthest nodes for best results in this configuration.
      1. As a result, I am assuming the termination in this case can be a small series resistor that would attenuate noise. These can be placed at the inputs of each node. Please note that ISO6741 does act as a re-driver since it operates recreates the signal after the isolation.
    3. 60cm is possible. Transmission delay will have a greater effect. Please make sure that it is acceptable for your application. The reference design you are referring to discussed how to account for trance and cable length. 
    4. The data section "3 Hardware, Software, Testing Requirements, and Test Results" suggests that there 60cm will achieve 10MHz SPI communication. However, note that LVDS will be more immune to noise and ground potential fluctuations. 

    Best,
    Andrew 

  • 0 in reply to Andrew J
    Prodigy 60 points

    Hello Andrew,

    1. I don't understand your answer. If you say 30 cm is possible, why do you say I have to take into account the transmission delay? Could you please provide me with some information or reference?
    2. When you say the best option is to have a small series resistor on the two farthest nodes, what do you mean? From your answer I understand that I have to put in E_A_(M-1) and E_A_M a series resistor on the MOSI and SCLK signals, is that what you mean? Do you have any information on how I can calculate this resistor?
    3. I will carefully review the tidued8 document, but I don't recall anything about trace length other than the recommendation to keep the same trace length between MISO and SCLK2 (SCLK returned) to eliminate trace delay (p. 8). Is that what you are telling me to keep in mind?
    4. Yes, the higher noise immunity is one of the reasons I was thinking of using the SPI+LVDS approach. However, I would like to confirm if single-ended SPI would also be possible and decide with my team the optimal approach.

    On the other hand, could you provide me the main documents for LVDS design? I have found slla014a, slla038b, tidued8 and slla108a (for M-LVDS) but I'm not sure if there are more.

    Thank you very much for your help.

  • 0 in reply to Rafael Savariego
    Guru 317250 points

    A rough estimate is 1 pf per cm of trace. Don't forget the traces on the daughter boards, and the connectors usually have a higher capacitance.

    Source termination is a series resistor at the driver. The sum of the driver's output impedance and the resistor should match the characteristic impedance of the trace (usually 50 Ω). (As far as I can see, the ISO6741 has very weak outputs with an impedance of about 50 Ω, so you don't need to do anything.)

    Series resistors at the receiver have no effect on the signal quality.

    The delay between the edges of the clock signal and of the MISO signal (as received at the master) is double the transmission delay. (A rough estimate for normal traces is 50 ps/cm.)

  • 0 in reply to Clemens Ladisch
    TI__Mastermind 29375 points

    Hello Rafael, 

    Sorry for the confusion. 

    What I mean is that the SPI signal should be able to transmit successfully over 30cm and 60cm traces. There will likely not be an issue on the physical layer.

    From a protocol standpoint it is important to make sure that transmission delay is taken into account since the data lines will be affected by propagation delay twice (send and receive) while the SCLK line is only affected once. 

    In short, SPI would be a possible solution, however SPI+LVDS will be more robust due to the differential signaling. 

  • 0 in reply to Andrew J
    Prodigy 60 points

    Hello Andrew and Clemens,

    Yes, I understand what you are saying about MISO and SCLK transmission delay, it is explained in the tidued8 document and solved by using two separate SPI controllers (one as master and one as slave) and a feedback from SCLK as SCLK2.

    Last question before close that thread, could you provide any technical reference about termination of transmission lines?

    Thank you very much for both answers, I will have an discussion with my team about the solution we will adopt (SPI or SPI+LVDS).

  • +1 in reply to Rafael Savariego
    Guru 317250 points

    See page 1-27 of the LVC Designer's Guide; source termination is technique 4.

  • 0 in reply to Clemens Ladisch
    Prodigy 60 points

    Thank you very much. I will close the issue.

  • 0 in reply to Rafael Savariego
    Prodigy 75 points

    Suggest testing EFT and ESD, longer SPI and LVDS may be problematic