Tool/software:
Hello, in our product we changed from another vendor to TI's ISO. But with prototypes we found TI uses internal states between "unrelated" SPI transfers. We use ISO in SPI only non-daisy mode.
I mean "address" and "data" phases. It may happen that the CPU will come 'out of sync' with ISO chip. There are several reasons (not related to ISO).
Using RST pin will not help, since it is too slow.
So, my question is: how exactly does the state machine works for ADDRESS/DATA phase ? Just "like flip/flop" driven by CS - so we need to keep CPU in sync ?
Is there any way to 'reset' the machine or 'get' information about which phase it is ? Imagine there is a spurious 'CS' toggle for example (no CLK activity). In previous vendor 'CS UP' resets internal machine (as expected). But this chip (all others things works perfectly) adds internal state memory and this spurious toggle make chip out-of-order.
Any idea how to fix/proceed ? We can't guarantee sync with ISO forever and ever before power will be disconnected :)
There is nothing interested in the schematic, everything works well (r/w/inputs/...). Except falling out of sync. In this case 'CS' toggle solves the problem - but how to detect when.
As the result - we would like to 'read' internal state (address or data) or reset to 'address'.
Thank you !
