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ISOW7741: EN_IO1 also puts other side outputs to default state? Problem in SPI isolation

Erki Leitaru
Prodigy 20 points

Part Number: ISOW7741
Other Parts Discussed in Thread: SN74LVC1G125

Hi. As I understood from datasheet, pulling EN_IO1  should disable only the OUTD pin. So I can use the isolator to put many SPI devices in parallel if I route their MISO signal through this pin.

What I found out, if I pull EN_IO1 low, the other side signals go also to their default state. I used CS with inverter to drive EN_IO1.

Now the communication fails because clock goes to illegal state and bits are offset. Then I replaced the device with -F device only to realize that now the other side CS goes also low with other pins. Fail again.

Is it itended behaviour or the chip has just a bug in its design? 

  • +1
    Guru 326020 points

    Table 9-3 says:

    A low value of output enable causes the outputs of the same side to be high impedance and the output of opposite side to be fail-safe default state.

    To disable only one signal, route it through a separate three-state buffer (e.g., SN74LVC1G125). Alternatively, combine multiple default-high signals with an AND gate.