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ISO7760: Need clarification for "undetermined" output state

Jeff Colter0
Prodigy 30 points
Part Number: ISO7760


Hi,

The data sheet for the ISO77XX family has a truth table (see below) with a footnote (3), regarding intermediate supply voltages, between 1.7 and 2.25 V, where the output is in an "undetermined" state.

Can I assume that means it's neither a guaranteed high or low but not exactly "high impedance", and that a pull down resistor on the output would pull it reliably low?

I want to be sure there's no set of conditions where supply voltages ramping up and down can cause a false "solid on" condition.

Can someone clarify what undetermined really means?

Thanks,

Jeff

  • 0
    TI__Guru 55885 points
    Hi Jeff,

    Thank you for showing interest in ISO77xx device family.
    When VCCO is between 1.7V and 2.25V, the device is in the transition from power-down state to power-up state. Hence the outputs are expected to be in high impedance if device is still in power down state but will be in a definite logic state if it has powered-up. This is the reason for stating it as undetermined.

    I hope that answers your question, thank you.


    Regards,
    Koteshwar Rao
  • 0 in reply to Koteshwar Rao
    Prodigy 30 points
    Thanks!

    So, just to be sure, if the input is low and VCCI is powering up or down, and VCCO is powered up, there's no way you'll get a logic high on the output. The high-Z state on the output can be pulled reliably low with a resistor, I presume.
  • 0 in reply to Jeff Colter0
    TI__Guru 55885 points
    Hi Jeff,

    I am not sure if the point I was trying to make in my earlier post is perceived the way I meant it to be. Please allow me to clarify further.

    1. When VCCO is PU and VCCI is PD, the output function is defined in the function table. Similarly when VCCO is PU and VCCI is PU, the output function is also defined in the function table and is straight forward.

    2. When VCCO (and not VCCI) is between 1.7V and 2.25V, the output channel transitions from PD to PU and it can happen at any single voltage point between 1.7V and 2.25V.

    3. When VCCO is moving from 1.7V to 2.25V, the output channel is in PD before the transition and is in PU after the transition.

    4. Under this condition, when the output channel is in PD the state at output is going to be Hi-Z. When the output channel is PU the state at output is going to follow the function table with VCCO = PU.

    Hopefully this clarifies your question. If you are looking to avoid any particular state or condition, please do share the requirement and I will try to propose a solution. Thank you.


    Regards,
    Koteshwar Rao